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? 2016 microchip technology inc. ds00002164b-page 1 highlights single-chip ethernet physical layer transceiver (phy) comprehensive flexpwr ? technology - flexible power management architecture - lvcmos variable i/o voltage range: +1.6v to +3.6v - integrated 1.2v regulator with disable feature hp auto-mdix support small footprint 32-pin qfn/sqfn lead-free rohs compliant packages (5 x 5mm) target applications set-top boxes networked printers and servers test instrumentation lan on motherboard embedded telecom applications video record/playback systems cable modems/routers dsl modems/routers digital video recorders ip and video phones wireless access points digital televisions digital media adapters/servers gaming consoles poe applications (refer to application note 17.18) key benefits high-performance 10/100 ethernet transceiver - compliant with ieee802.3/802.3u (fast ethernet) - compliant with is o 802-3/ieee 802.3 (10base-t) - loop-back modes - auto-negotiation - automatic polarity detection and correction - link status change wake-up detection - vendor specific register functions - supports both mii and the reduced pin count rmii interfaces power and i/os - various low power modes - integrated power-on reset circuit - two status led outputs - latch-up performance exceeds 150ma per eia/jesd 78, class ii - may be used with a single 3.3v supply additional features - ability to use a low cost 25mhz crystal for reduced bom packaging - 32-pin qfn/sqfn (5x5 mm) lead-free rohs compliant package with mii and rmii environmental - extended commercial temperature range ? (0c to +85c) - industrial temperature range version avail - able (-40c to +85c) lan8710a/lan8710ai small footprint mii/rmii 10/100 ethernet transceiver with hp auto-mdix and flexpwr ? technology downloaded from: http:///
to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunication s department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur - rent devices. as device/doc umentation issu es become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a pa rticular device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please spec ify wh ich device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. lan8710a/lan8710ai ds00002164b-page 2 ? 2016 microchip technology inc. downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 3 lan8710a/lan8710ai table of contents 1.0 introduction ..................................................................................................................................................................................... 4 2.0 pin description and configuration .................................................................................................................................................. 6 3.0 functional description .................................................................................................... .............................................................. 16 4.0 register descriptions .................................................................................................................................................................... 43 5.0 operational charac teristics ............................................................................................... ............................................................ 54 6.0 package information ..................................................................................................................................................................... 68 7.0 application notes ......................................................................................................... ................................................................. 73 appendix a: data sheet revision history ........................................................................................................................................... 75 the microchip web site ........................................................................................................ .............................................................. 76 customer change notification service ............................................................................................................................................... 76 customer support ............................................................................................................................................................................... 76 product identification system ................................................................................................. ............................................................ 77 downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 4 ? 2016 microchip technology inc. 1.0 introduction 1.1 general terms and conventions the following is list of the general terms used throughout this document: byte 8-bits fifo first in first out buffer; often used for elasticity buffer mac media access controller mii media independent interface rmii? reduced media independent interface tm n/a not applicable x indicates that a logic state is dont care or undefined. reserved refers to a reserved bit field or address. unless otherwise no ted, reserved bits must always be zero for write opera - tions. unless otherwise noted, values are not guaranteed when reading reserved bits. unless otherwise noted, do not read or write to reserved addresses. smi serial management interface 1.2 general description the lan8710a/lan8710ai is a low-power 10base-t/100base- tx physical layer (phy) transceiver with variable i/o voltage that is compliant with the ieee 802.3-2005 standards. the lan8710a/lan8710ai supports communication with an eth ernet mac via a standard mii (ieee 802.3u)/rmii inter - face. it contains a full-duplex 10-base-t/100base-tx tran sceiver and supports 10mbps (10base-t) and 100mbps (100base-tx) operation. the lan8710a/lan 8710ai implements auto-negotiation to automatically determine the best possible speed and duplex mode of operation. hp auto-mdix support allows the use of direct connect or cross-over lan cables. the lan8710a/lan8710ai s upport s both ieee 802.3-2005 compliant and vendor-specif ic register functions. however, no register access is required for operation. the initial co nfiguration may be selected vi a the configuration pins as described in section 3.7, "configuration straps," on page 29 . register-selectable configuration options may be used to further define the functionality of the transceiver. per ieee 802.3-2005 standards, all digital interface pins are tole rant to 3.6v. the device can be configured to operate on a single 3.3v supply utilizing an integrated 3.3v to 1.2v linear regulator. the linear regulator may be optionally dis - abled, allowing usage of a high efficiency external regulator for lower system power dissipation. the lan8710a/lan8710ai is available in both extended comm e rcial and industrial temperature range versions. a typ - ical system application is shown in figure 1-1 . downloaded from: http:///
figure 1-1: system block diagram lan8710a/ lan8710ai 10/100 ethernet mac mii/ rmii mode led transformer crystal or clock oscillator mdi rj45 figure 1-2: architectural overview rmii/mii logic interrupt generator leds pll receiver dsp system: clock data recovery equalizer squeltch & filters analog-to- digital 10m rx logic 100m rx logic 100m pll 10m pll transmitter 10m transmitter 100m transmitter 10m tx logic 100m tx logic central bias phy address latches lan8710a/lan8710ai rbias led1 nint xtal2 xtal1/clkin led2 management control mode control reset control mdix control hp auto-mdix rxp/rxn txp/txn txd[0:3] txen txer txclk rxd[0:3] rxdv rxer rxclk crs col/crs_dv mdc mdio auto- negotiation rmiisel nrst mode[0:2] smi phyad[0:2] ? 2016 microchip technology inc. ds00002164b-page 5 lan8710a/lan8710ai downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 6 ? 2016 microchip technology inc. 2.0 pin description and configuration figure 2-1: 32-qfn/sqfn pin assignments (top view) vss note: exposed pad (vss) on bottom of package must be connected to ground lan8710a/lan8710ai (top view) mdio 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 txd3 rxdv vdd1a txn txp rxn rxp rbias col/crs_dv/mode2 crs rxer/rxd4/phyad0 vddio rxd0/mode0 rxd1/mode1 rxd2/rmiisel note 2-1 when a lower case n is used at the beginning of t he signal name, it indicates that the signal is active low. for example, nrst indicates that the reset signal is active low. note 2-2 the buf fer type for each signal is indicated in the buffer type co lumn. a descripti on of the buffer types is provided in section 2.2 . downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 7 lan8710a/lan8710ai table 2-1: mii/rmii signals num pins name symbol buffer type description 1 transmit data 0 txd0 vis the mac transmits data to the transceiver using this signal in all modes. 1 transmit data 1 txd1 vis the mac transmits data to the transceiver using this signal in all modes. 1 transmit data 2 (mii mode) txd2 vis the mac transmits data to the transceiver using this signal in mii mode. note: this signal must be grounded in rmii mode. 1 transmit data 3 (mii mode) txd3 vis the mac transmits data to the transceiver using this signal in mii mode. note: this signal must be grounded in rmii mode. 1 interrupt out - put nint vo8 active low interrupt output. place an external resistor pull-up to vddio. note: refer to section 3.6, "interrupt management," on page 27 for additional details on device interrupts. note: refer to section 3.8.1.2, "nintsel and led2 polarity selection," on page 33 for details on how the nintsel configuration strap is used to determine the function of this pin. transmit error (mii mode) txer vis (pu) when driven high, the 4b/5b encode process substitutes the transmit error code-group (/h/) for the encoded data word. this input is ignored in the 10base-t mode of operation. transmit data 4 (mii mode) txd4 vis (pu) in symbol interface (5b decoding) mode, this sig - nal becomes the mii transmit data 4 line (the msb of the 5-bit symbol code-group). note: this signal is not used in rmii mode. 1 transmit enable txen vis (pd) indicates that valid transmission data is present on txd[3:0]. in rmii mode , only txd[1:0] provide valid data. 1 transmit clock (mii mode) txclk vo8 used to latch data from the mac into the trans - ceiver. mii (100base-tx): 25mhz mii (10base-t): 2.5mhz note: this signal is not used in rmii mode. downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 8 ? 2016 microchip technology inc. 1 receive data 0 rxd0 vo8 bit 0 of the 4 (2 in rmii mode) data bits that are sent by the transceiver on the receive path. phy operat - ing mode 0 configuration strap mode0 vis (pu) combined with mode1 and mode2, this config - uration strap sets t he default phy mode. see note 2-3 for more information on configura - tion straps. note: refer to section 3.7.2, "mode[2:0]: mode configuration," on page 30 for additional details. 1 receive data 1 rxd1 vo8 bit 1 of the 4 (2 in rmii mode) data bits that are sent by the transceiver on the receive path. phy operat - ing mode 1 configuration strap mode1 vis (pu) combined with mode0 and mode2, this config - uration strap sets t he default phy mode. see note 2-3 for more information on configura - tion straps. note: refer to section 3.7.2, "mode[2:0]: mode configuration," on page 30 for additional details. 1 receive data 2 (mii mode) rxd2 vo8 bit 2 of the 4 (in mii mode) data bits that are sent by the transceiver on the receive path. note: this signal is not used in rmii mode. mii/rmii mode select configuration strap rmiisel vis (pd) this configuration strap selects the mii or rmii mode of operation. wh en strapped low to vss, mii mode is selected. when strapped high to vddio rmii mode is selected. see note 2-3 for more information on configura - tion straps. note: refer to section 3.7.3, "rmiisel: mii/ rmii mode configuration," on page 31 for additional details. 1 receive data 3 (mii mode) rxd3 vo8 bit 3 of the 4 (in mii mode) data bits that are sent by the transceiver on the receive path. note: this signal is not used in rmii mode. phy address 2 configura - tion strap phyad2 vis (pd) combined with phyad0 and phyad1, this con - figuration strap sets the transceivers smi address. see note 2-3 for more information on configura - tion straps. note: refer to section 3.7.1, "phyad[2:0]: phy address configuration," on page 29 for additional information. table 2-1: mii/rmii signals (continued) num pins name symbol buffer type description downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 9 lan8710a/lan8710ai 1 receive error rxer vo8 this signal is asserted to indicate that an error was detected somewhere in the frame presently being transferred from the transceiver. note: this signal is optional in rmii mode. receive data 4 (mii mode) rxd4 vo8 in symbol interface (5b decoding) mode, this sig - nal is the mii receive data 4 signal, the msb of the received 5-bit symbol code-group. note: unless configured to the symbol interface mode, this pin functions as rxer. phy address 0 configuration strap phyad0 vis (pd) combined with phyad1 and phyad2, this con - figuration strap sets the transceivers smi address. see note 2-3 for more information on configura - tion straps. note: refer to section 3.7.1, "phyad[2:0]: phy address configuration," on page 29 for additional information. 1 receive clock (mii mode) rxclk vo8 in mii mode, this pin is the receive clock output. mii (100base-tx): 25mhz mii (10base-t): 2.5mhz phy address 1 configura - tion strap phyad1 vis (pd) combined with phyad0 and phyad2, this con - figuration strap sets the transceivers smi address. see note 2-3 for more information on configura - tion straps. note: refer to section 3.7.1, "phyad[2:0]: phy address configuration," on page 29 for additional information. 1 receive data valid rxdv vo8 indicates that recovered and decoded data is available on the rxd pins. table 2-1: mii/rmii signals (continued) num pins name symbol buffer type description downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 10 ? 2016 microchip technology inc. note 2-3 configuration strap values are latched on power-on reset a nd system reset. configuration straps are identified by an underlined symbol name. signals th at function as configuration straps must be augmented with an external resistor when connected to a load. refer to section 3.7, "configuration straps," on page 29 for additional information. 1 carrier sense / receive data valid (rmii mode) crs_dv vo8 this signal is asserted to indicate the receive medium is non-idle in rmii mode. when a 10base-t packet is received, crs_dv is asserted, but rxd[1:0] is held low until the sfd byte (10101011) is received. note: per the rmii standard, transmitted data is not looped back onto the receive data pins in 10base-t half-duplex mode. collision detect (mii mode) col vo8 this signal is asserted to indicate detection of a collision condition in mii mode. phy operat - ing mode 2 configuration strap mode2 vis (pu) combined with mode0 and mode1, this config - uration strap sets t he default phy mode. see note 2-3 for more information on configura - tion straps. note: refer to section 3.7.2, "mode[2:0]: mode configuration," on page 30 for additional details. 1 carrier sense (mii mode) crs vo8 (pd) this signal indicates detection of a carrier in mii mode. table 2-1: mii/rmii signals (continued) num pins name symbol buffer type description downloaded from: http:///
table 2-2: led pins num pins name symbol buffer type description 1 led 1 led1 o12 link activity led indication. this pin is driven a ctive when a valid link is detected and blinks when activity is detected. note: refer to section 3.8.1, "leds," on page 32 for additional led information. regulator off co nfiguration strap regoff is (pd) this configuration strap is used to disable the internal 1.2v regulator. when the regulator is dis - abled, external 1.2v must be supplied to vddcr. when regoff is pulled high to vdd2a with an external resistor, the internal regulator is disabled. when regoff is floating or pulled low, the internal regulator is enabled (default). see note 2-4 for more information on configura - tion straps. note: re fer to section 3.7.4, "regoff: internal +1.2v regulator configuration," on page 32 for additional details. 1 led 2 led2 o12 link speed led indication. this pin is driven a ctive when the operating speed is 100mbps. it is inactive when the operating speed is 10mbps or during line isolation. note: refer to section 3.8.1, "leds," on page 32 for additional led information. nint/txer/ txd4 function select configuration strap nintsel is (pu) this configuration strap selects the mode of the nint/txer/txd4 pin. when nintsel is floated or pulled to vdd2a, nint is selected for operation on the nint/txer/txd4 pin (default). when nintsel is pulled low to vss, txer/ txd4 is selected for operation on the nint/ txer/txd4 pin. see note 2-4 for more information on configura - tion straps. note: re fer to see section 3.8.1.2, "nintsel and led2 polarity selection," on page 33 for additional information. ? 2016 microchip technology inc. ds00002164b-page 11 lan8710a/lan8710ai note 2-4 configuration strap values are latched on power-on reset and system reset. configuration straps are identified by an underlined symbol name. signals th at function as configuration straps must be augmented with an external resistor when connected to a load. refer to section 3.7, "configuration straps," on page 29 for additional information. downloaded from: http:///
table 2-3: serial management interface (smi) pins num pins name symbol buffer type description 1 smi data input/ output mdio vis/ vod8 serial management interface data input/output 1 smi clock mdc vis serial management interface clock table 2-4: ethernet pins num pins name symbol buffer type description 1 ethernet tx/ rx positive channel 1 txp aio transmit/receive positive channel 1 1 ethernet tx/ rx negative channel 1 txn aio transmit/receive negative channel 1 1 ethernet tx/ rx po sitive channel 2 rxp aio transmit/receive positive channel 2 1 ethernet tx/ rx neg ative channel 2 rxn aio transmit/receive negative channel 2 table 2-5: miscellaneous pins num pins name symbol buffer type description 1 external cryst al input xtal1 iclk external crystal input external clock input clkin iclk single-ended clock oscillator input. note: w hen using a single ended clock oscillator, xtal2 should be left unconnected. 1 external cryst al out - put xtal2 oclk external crystal output 1 external reset nrst vis (pu) system reset. this signal is active low. lan8710a/lan8710ai ds00002164b-page 12 ? 2016 microchip technology inc. downloaded from: http:///
table 2-6: analog reference pins num pins name symbol buffer type description 1 external 1% bias resistor inpu t rbias ai this pin requires connection of a 12.1k ohm (1%) resistor to ground. refer to the lan8710a/lan8710ai reference sch ematic for connection information. note: the nominal voltage is 1.2v and the resistor will dissipate approximately 1mw of power. table 2-7: power pins num pins name symbol buffer type description 1 +1.6v to +3.6v vari - able i/o power vddio p +1.6v to +3.6v variable i/o power refer to the lan8710a/lan8710ai reference sch ematic for connection information. 1 +1.2v digital core power supp ly vddcr p supplied by the on-chip regulator unless config - ured for regulator off mode via the regoff con - figuration strap. refer to the lan8710a/lan8710ai reference schematic for connection information. note: 1 uf and 470 pf decoupling capacitors in parallel to ground should be used on this pin. 1 +3.3v chan - nel 1 analog port power vdd1a p +3.3v analog port power to channel 1 refer to the lan8710a/lan8710ai reference sch ematic for connection information. 1 +3.3v chan - nel 2 analog port power vdd2a p +3.3v analog port power to channel 2 and the i nternal regulator. refer to the lan8710a/lan8710ai reference sch ematic for connection information. 1 ground vss p common ground. this exposed pad must be con - nected to the ground plane with a via array. ? 2016 microchip technology inc. ds00002164b-page 13 lan8710a/lan8710ai downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 14 ? 2016 microchip technology inc. 2.1 pin assignments table 2-8: 32-qfn package pin assignments pin num pin name pin num pin name 1 vdd2a 17 mdc 2 led2/ nintsel 18 nint/txer/txd4 3 led1/ regoff 19 nrst 4 xtal2 20 txclk 5 xtal1/clkin 21 txen 6 vddcr 22 txd0 7 rxclk/ phyad1 23 txd1 8 rxd3/ phyad2 24 txd2 9 rxd2/ rmiisel 25 txd3 10 rxd1/ mode1 26 rxdv 11 rxd0/ mode0 27 vdd1a 12 vddio 28 txn 13 rxer/rxd4/ phyad0 29 txp 14 crs 30 rxn 15 col/crs_dv/ mode2 31 rxp 16 mdio 32 rbias 2.2 buffer types table 2-9: buffer types buffer type description is schmitt-triggered input o12 output with 12ma sink and 12ma source vis variable voltage schmitt-triggered input vo8 variable voltage output with 8ma sink and 8ma source vod8 variable voltage open-drain output with 8ma sink pu 50ua (typical) internal pull-up. unless otherwise no ted in the pin description, internal pull- ups are always enabled. note: internal pull-up resistors prevent unconnec ted inputs from floatin g. do not rely on internal resistors to drive signals external to the device. when connected to a load that must be pulled high, an ex ternal resistor must be added. downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 15 lan8710a/lan8710ai note 2-5 the digital signals are not 5v tolerant. refer to section 5.1, "absolute maximum ratings*," on page 54 for additional buffer information. note 2-6 sink and source capabilities are dependent on the vddio voltage. refer to section 5.1, "absolute maximum ratings*," on page 54 for additional information. pd 50ua (typical) internal pull-down. unless otherw ise noted in the pin description, internal pull- downs are always enabled. note: internal pull-down resistors prevent unconnec ted inputs from floating. do not rely on internal resistors to drive signals external to the device. when connected to a load that must be pulled low, an external resistor must be added. ai analog input aio analog bi-directional iclk crystal oscillator input pin oclk crystal oscillator output pin p power pin table 2-9: buffer types (continued) buffer type description downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 16 ? 2016 microchip technology inc. 3.0 functional description this chapter provides functional descrip tions of the various device features. these features have be en categorized into the following sections: transceiver auto-negotiation hp auto-mdix support mac interface serial management interface (smi) interrupt management configuration straps miscellaneous functions application diagrams 3.1 transceiver 3.1.1 100base-tx transmit the 100base-tx transmit data path is shown in figure 3-1 . each major block is explained in the following subsections. figure 3-1: 100base-tx transmit data path mac tx driver mlt-3 converter nrzi converter 4b/5b encoder cat-5 rj45 25mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 scrambler and piso mii/rmii 25mhz by 4 bits ext ref_clk (for rmii only) pll mii 25 mhz by 4 bits or rmii 50mhz by 2 bits mlt-3 magnetics 125 mbps serial tx_clk (for mii only) 3.1.1.1 100base-tx transmit data across the mii/rmii interface for mii, the mac controller drives the transmit data onto the txd bus and asserts txen to indicate valid data. the data is latched by the transceivers mii block on the rising edge of txclk. the data is in the form of 4-bit wide 25mhz data. for rmii, the mac controller dr ives the transmit data onto the txd bus and asserts txen to indicate valid data. the data is latched by the transceivers rmii block on the rising edge of ref_clk. the data is in the form of 2-bit wide 50mhz data. 3.1.1.2 4b/5b encoding the transmit data passes from the mii/rmii block to the 4b/5b encoder. this block encodes the data from 4-bit nibbles to 5-bit symbols (known as code-groups) according to ta b l e 3-1 . each 4-bit data-nibble is mapped to 16 of the 32 pos - sible code-groups. the remaining 16 code-groups are ei ther used for control information or are not valid. downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 17 lan8710a/lan8710ai the first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through f. the remaining code-groups are given letter designations with slashe s on either side. for example, an idle code-group is / i/, a transmit error code-group is /h/, etc. table 3-1: 4b/5b code table code group sym receiver interpretation transmitter interpretation 11110 0 0 0000 data 0 0000 data 01001 1 1 0001 1 0001 10100 2 2 0010 2 0010 10101 3 3 0011 3 0011 01010 4 4 0100 4 0100 01011 5 5 0101 5 0101 01110 6 6 0110 6 0110 01111 7 7 0111 7 0111 10010 8 8 1000 8 1000 10011 9 9 1001 9 1001 10110 a a 1010 a 1010 10111 b b 1011 b 1011 11010 c c 1100 c 1100 11011 d d 1101 d 1101 11100 e e 1110 e 1110 11101 f f 1111 f 1111 11111 i idle sent after /t/r until txen 11000 j first nibble of ssd, translated to 0101 following idle, else rxer sent for rising txen 10001 k second nibble of ssd, translated to 0101 following j, else rxer sent for rising txen 01101 t first nibble of esd, causes de-assertion of crs if followed by /r/, else assertion of rxer sent for falling txen 00111 r second nibble of esd, causes deasser - tion of crs if following /t/, else assertion of rxer sent for falling txen 00100 h transmit error symbol sent for rising txer 00110 v invalid, rxer if during rxdv invalid 11001 v invalid, rxer if during rxdv invalid 00000 v invalid, rxer if during rxdv invalid 00001 v invalid, rxer if during rxdv invalid downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 18 ? 2016 microchip technology inc. 3.1.1.3 scrambling repeated data patterns (especially the idle code-group) ca n have power spectral densities with large narrow-band peaks. scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire channel bandwidth. this uniform spectral density is required by fcc regulations to prevent excessive emi from being radiated by the physical wiring. the seed for the scrambler is gener ated from the transceiver address, phyad , ensuring that in multiple-transceiver applications, such as repeaters or switches, each transceiver wi ll have its own scrambler sequence. the scrambler also performs the parallel in serial out conversion (piso) of the data. 3.1.1.4 nrzi and mlt-3 encoding the scrambler block passes the 5-bit wide parallel data to the nrzi converter where it becomes a serial 125mhz nrzi data stream. the nrzi is encoded to mlt-3. mlt-3 is a tri- level code where a change in the logic level represents a code bit 1 and the logic output remaining at the same level represents a code bit 0. 3.1.1.5 100m transmit driver the mlt3 data is then passed to the analog transmitter, whic h drives the differential mlt-3 signal, on outputs txp and txn, to the twisted pair media across a 1:1 ratio isol ation transformer. the 10base-t and 100base-tx signals pass through the same transformer so that common magnetics ca n be used for both. the transmitter drives into the 100 ? impedance of the cat-5 cable. cable termination a nd impedance matching require external components. 3.1.1.6 100m phase lock loop (pll) the 100m pll locks onto reference clock and generates the 125mhz clock used to drive the 125 mhz logic and the 100base-tx transmitter. 00010 v invalid, rxer if during rxdv invalid 00011 v invalid, rxer if during rxdv invalid 00101 v invalid, rxer if during rxdv invalid 01000 v invalid, rxer if during rxdv invalid 01100 v invalid, rxer if during rxdv invalid 10000 v invalid, rxer if during rxdv invalid table 3-1: 4b/5b code table (continued) code group sym receiver interpretation transmitter interpretation downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 19 lan8710a/lan8710ai 3.1.2 100base-tx receive the 100base-tx receive dat a path is shown in figure 3-2 . each major block is explained in the following subsections. figure 3-2: 100base-tx receive data path mac a/d converter mlt-3 converter nrzi converter 4b/5b decoder magnetics cat-5 rj45 pll mii 25mhz by 4 bits or rmii 50mhz by 2 bits rx_clk (for mii only) 25mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 6 bit data descrambler and sipo 125 mbps serial dsp: timing recovery, equalizer and blw correction mlt-3 mii/rmii 25mhz by 4 bits ext ref_clk (for rmii only) 3.1.2.1 100m receive input the mlt-3 from the cable is fed into the transceiver (on inputs rxp and rxn) via a 1:1 ratio transformer. the adc samples the incoming differential signal at a rate of 125m sa mples per second. using a 64-level quanitizer, it generates 6 digital bits to represent each sample. the dsp adjusts the gain of the adc according to the observed signal levels such that the full dynamic range of the adc can be used. 3.1.2.2 equalizer, baseline wander correction and clock and data recovery the 6 bits from the adc are fed into the dsp block. the equalizer in the dsp section compensates for phase and ampli - tude distortion caused by the physical channel consisting of magnetics, connectors, and cat- 5 cable. the equalizer can restore the signal for any good-qua lity cat-5 cable between 1m and 150m. if the dc content of t he sig nal is such that the low-frequency comp onents fall below the low frequency pole of the iso - lation transformer, then the droop characteristics of the tran sformer will become significant and baseline wander (blw) on the received signal will result. to prevent corruption of the received data, the transceiver corrects for blw and can receive the ansi x3.263-1995 fddi tp-pmd defined killer packet with no bit errors. the 100m pll generates multiple phases of the 125mhz clock. a multip lexer, controlled by the ti ming unit of the dsp, selects the optimum phase for sampling the data. this is used as the received recovered clo ck. this clock is used to extract the serial data from the received signal. 3.1.2.3 nrzi and mlt-3 decoding the dsp generates the mlt-3 recovered le vels that are fed to the mlt-3 converter. the mlt-3 is then converted to an nrzi data stream. 3.1.2.4 descrambling the descrambler performs an inverse function to the scrambler in the transmitter and also performs the serial in parallel out (sipo) conversion of the data. during reception of idle (/i/) symbols. the descrambler synchronizes its descrambl er key to the incoming stream. once synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data. downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 20 ? 2016 microchip technology inc. special logic in the descrambler ensures synchronization with the remote transceiver by searching for idle symbols within a window of 4000 bytes (40us). this window ensures that a maximum packet size of 1514 bytes, allowed by the ieee 802.3 standard, can be received wi th no interference. if no idle-symbols are detected within this time-period, receive operation is aborted and the descram bler re-starts the synchronization process. 3.1.2.5 alignment the de-scrambled signal is then aligned into 5-bit code-grou ps by recognizing the /j/k/ st art-of-stream delimiter (ssd) pair at the start of a packet. once the code-word alignment is determined, it is stored and ut ilized until the next start of frame. 3.1.2.6 5b/4b decoding the 5-bit code-groups are translated into 4-bit data nibble s according to the 4b/5b table. the translated data is pre - sented on the rxd[3:0] signal lines. the ssd, /j/k/, is translated to 0101 0101 as the first 2 nibbles of the mac pre - amble. reception of the ssd causes the tr ansceiver to assert the receive data valid signal, indicating that valid data is available on the rxd bus. successive valid code-groups are tr anslated to data nibbles. reception of either the end of stream delimiter (esd) consisting of the /t/r/ symbols, or at least two /i/ symbol s causes the transceiver to de-assert the carrier sense and receive data valid signals. note: th ese symbols are not translated into data. 3.1.2.7 receive data valid signal the receive data valid signal (rxdv) indicates that recovered and decoded nibbles are being presented on the rxd[3:0] outputs synchronous to rxclk. rxdv becomes active after the /j/k / delimiter has been recognized and rxd is aligned to nibble boundaries. it remains active until either the /t/r/ delimiter is recognized or link test indicates failur e or sigdet becomes false. rxdv is asserted when the first nibble of tra nslated /j/k/ is ready for transfe r over the media independent interface (mii mode). figure 3-3: 5d 5 data data data data rxd rx_dv rx_clk 5d 5 data data data data clear-text 5 jk 5 55 tr idle relationship between received data and specific mii signals 3.1.2.8 receiver errors during a frame, unexpected code-groups are considered rece ive errors. expected code groups are the data set (0 through f), and the /t/r/ (esd) symbol pair. when a receive error occurs, the rxer signal is asserted and arbitrary data is driven onto the rxd[3:0] lines. should an error be detected during the time that the /j/k/ delimiter is being decoded (bad ssd error), rxer is asserted true and the value 1110 is driven onto the rxd[ 3:0] lines. note that the valid data signal is not yet asserted when the bad ssd error occurs. 3.1.2.9 100m receive data across the mii/rmii interface in mii mode, the 4-bit data nibbles are sent to the mii block. these data nibbles are clocked to the controller at a rate of 25mhz. the controller samples the data on the rising edge of rxclk. to ensure that the setup and hold requirements are met, the nibbles are clocked out of the transceiver on th e falling edge of rxclk. rxclk is the 25mhz output clock for the mii bus. it is recovered from the received data to clock the rxd bus. if there is no received signal, it is derived from the system referenc e clock (xtal1/clkin). when tracking the received data, rxclk has a maximum jitter of 0 .8ns (provided that the jitte r of the input clock, xtal1/ clkin, is below 100ps). downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 21 lan8710a/lan8710ai in rmii mode, the 2-bit data nibbles are sent to the rmii block. these data nibbles are clocked to the controller at a rate of 50mhz. the controller samples the data on the rising edge of xtal1/clkin (ref_clk). to ensure that the setup and hold requirements are met, the nibbles are clocked ou t of the transceiver on the falling edge of xtal1/clkin (ref_clk). 3.1.3 10base-t transmit data to be transmitted comes from the mac layer controller . the 10base-t transmitter receiv es 4-bit nibbl es from the mii at a rate of 2.5mhz and converts them to a 10mbps seri al data stream. the data stream is then manchester-encoded and sent to the analog transmitter, which drives a sign al onto the twisted pair vi a the external magnetics. the 10m transmitter uses the following blocks: mii (digital) tx 10m (digital) 10m transmitter (analog) 10m pll (analog) 3.1.3.1 10m transmit data across the mii/rmii interface the mac controller drives the transmit da ta onto the txd bus. for mii, when th e controller has driven txen high to indicate valid data, the data is latched by the mii block on the rising edge of txclk. the data is in the form of 4-bit wide 2.5mhz data. for rmii, txd[1:0] shall transition synchronously with respect to ref_clk. when txen is asserted, txd[1:0] are accepted for transm ission by the device. txd[1:0] shall be 00 to indicate idle when txen is deasserted. values of txd[1:0] other than 00 when txen is deassert ed are reserved for out-of-band signaling (to be defined). values other than 00 on txd[1:0] while txen is deasserted shall be ignored by the device.txd[1:0] shall provide valid data for each ref_clk period while txen is asserted. in order to comply with legacy 10base-t mac/controllers, in half-duplex mo de the transceiver loops back the trans - mitted data, on the receive path. this does not confuse th e mac/controller since the co l signal is not asserted during this time. the transceiver also supports the sqe (heartbeat) signal. see section 3.8.7, "collision detect," on page 35 , for more details. 3.1.3.2 manchester encoding the 4-bit wide data is sent to the 10m tx block. the nibbles are converted to a 10mbps serial nrzi data stream. the 10m pll locks onto the exte rnal clock or internal oscill ator and produces a 20mhz clock. this is used to manchester encode the nrz data stream. when no data is being transmitted (txen is low), the 10m tx block outputs normal link pulses (nlps) to maintain communications with the remote link partner. 3.1.3.3 10m transmit drivers the manchester encoded data is sent to the analog transm itter where it is shaped and filtered before being driven out as a differential signal across the txp and txn outputs. 3.1.4 10base-t receive the 10base-t receiver gets the manchester- encoded analog sign al from the cable via the magnetics. it recovers the receive clock from the signal and uses th is clock to recover the nrzi data stream. this 10m serial data is converted to 4-bit data nibbles which are passed to the controller via mii at a rate of 2.5mhz. this 10m receiver uses the following blocks: filter and squelch (analog) 10m pll (analog) rx 10m (digital) mii (digital) 3.1.4.1 10m receive input and squelch the manchester signal from the cable is fed into the transceiver (on inputs rxp and rxn) via 1:1 rati o magnetics. it is first filtered to reduce any out-of-band noise. it then passes through a squel ch circuit. the squelch is a set of amplitude and timing comparators that norm ally reject differential voltage levels below 300mv and detect and recognize differential voltages above 585mv. downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 22 ? 2016 microchip technology inc. 3.1.4.2 manchester decoding the output of the squelch goes to the 10 m rx block where it is validated as manchester encoded data. the polarity of the signal is also checked. if the pol arity is reversed (local rxp is connected to rxn of the remote partner and vice versa), the condition is identified and corrected. the reversed condition is indicated by the xpol bit of the special con - trol/status indications register . the 10m pll is locked onto the received manchester signal, from which the 20mhz cock is generated. using this clock, t he manchester encoded data is extract ed and converted to a 10mhz nrzi data stream. it is then converted from serial to 4-bit wide parallel data. the 10m rx block also detects valid 10base-t idle signals - normal link pulses (nlps) - to maintain the link. 3.1.4.3 10m receive data acro ss the mii/rmii interface for mii, the 4-bit data nibbles are sent to the mii block. in mii mode, these data nibbles are valid on the rising edge of the 2.5 mhz rxclk. for rmii, the 2-bit data nibbles are sent to the rmii block. in rmii mode, these data nibbles are valid on the rising edge of the rmii ref_clk. 3.1.4.4 jabber detection jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition, which results in holding the t xen input for a long period. special logic is used to detect the jabber state and abort the transmission to the line within 45ms. once txen is deasserted, the logic resets the jabber condition. as shown in section 4.2.2, "basic status register," on page 45 , the jabber detect bit indicates that a jabber condition was detected. 3.2 auto-negotiation the purpose of the auto-ne gotiation function is to automat ically configure the transceiver to the optimum link parameters based on the capabilities of its link pa rtner. auto-negotiation is a mechanism fo r exchanging configuration information between two link-partners and automatical ly selecting the highest performance mode of operation supported by both sides. auto-negotiation is fully defined in clause 28 of the ieee 802.3 specification. once auto-negotiation has completed, information about the resolved link can be passed back to the controller via the serial management interface (smi ). the results of the negotiation process are reflected in the speed indication bits of the phy special control/status register , as well as in the auto negotiation link partner ability register . the auto-nego - tiation protocol is a purely physical layer activi ty and proceeds independent ly of the mac controller. the advertised capabilities of the transceiver are stored in the auto negotiation advertisement register . the default advertised by the transceiver is determined by user-defined on-chip signal options. the following blocks are activated during an auto-negotiation session: auto-negotiation (digital) 100m adc (analog) 100m pll (analog) 100m equalizer/blw/clock recovery (dsp) 10m squelch (analog) 10m pll (analog) 10m transmitter (analog) when enabled, auto-negotiation is started by the occurrence of one of the following events: hardware reset software reset power-down reset link status down setting the restart auto-negotiate bit of the basic control register downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 23 lan8710a/lan8710ai on detection of one of these events, the transceiver begins auto-negotiation by transmitting bursts of fast link pulses (flp), which are bursts of link pulses from the 10m transmitter. they are shaped as normal link pulses and can pass uncorrupted down cat-3 or cat-5 cable. a fast link pulse burst consists of up to 33 pulses. the 17 odd-numbered pulses, which are always present, frame the flp burst. the 16 even-numbered puls es, which may be present or absent, contain the data word being transmitted. presence of a dat a pulse represents a 1, while absence represents a 0. the data transmitted by an flp burst is known as a link code word . these are defined full y in ieee 802. 3 clause 28. in summary, the transceiver advertises 802.3 compliance in its se lector field (the first 5 bits of the link code word). it advertises its technology ability a ccording to the bits set in the auto negotiation advertisement register . there are 4 possible matches of the technology abilities. in the order of priority these are: 100m full duplex (highest priority) 100m half duplex 10m full duplex 10m half duplex (lowest priority) if the full capabilities of the transceiver are advertised (100 m, full duplex), and if the link partner is capable of 10m and 100m, then auto-negotiation selects 100m as the highest performance mode. if the link partner is capable of half and full duplex modes, then auto-negotiation selects fu ll duplex as the highest performance operation. once a capability match has been determined, the link code words are repeated with the acknowledge bit set. any dif - ference in the main content of the link code words at this time will cause auto-negotiation to re-start. auto-negotiation will also re-start if not all of the required flp bursts are received. the capabilities advertised during auto-negotiation by the tran sceiver are initially determined by the logic levels latched on the mode[2:0] configuration straps after reset completes. these configuration straps can also be used to disable auto-negotiation on power-up. refer to section 3.7.2, "mode[2:0]: mode configuration," on page 30 for additional infor - mation. writing the bits 8 through 5 of the auto negotiation advertisement register allows software control of the capabilities advertised by the transceiver. writing the auto negotiation advertisement register does not automatically re-start auto- negotiation. the restart auto-negotiate bit of the basic control register must be set before the new abilities will be advertised. auto-negotiation can also be disabled via software by clearing the auto-negotiation enable bit of the basic control register . note: the device does not support next page capability. 3.2.1 parallel detection if the lan8710a/lan8710ai is connected to a device lacking the ability to auto-negotiate (for example, no flps are detected), it is able to determine the speed of the link based on either 100m mlt-3 symbols or 10m normal link pulses. in this case the link is presumed to be half duplex per t he ieee standard. this ability is known as parallel detection. this feature ensures interoperability with legacy link partne rs. if a link is formed via parallel detection, then the link part - ner auto-negotiation able bit of the auto negotiation expansion register is cleared to indicate that the link partner is not capable of auto-negotiation. the controller has access to this information via the management interface. if a fault occurs during parallel detection, the parallel detection fault bit of link partner auto-negotiation able is set. auto negotiation link partner ability register is used to store the link partner ability information, which is coded in the received flps. if the link partner is not auto-negotiation capable, then the auto negotiation link partner ability register is updated after completion of parallel detection to reflect the speed capability of the link partner. 3.2.2 restarting auto-negotiation auto-negotiation can be restart ed at any time by setting the restart auto-negotiate bit of the basic contro l register . auto-negotiation will also restart if the link is broken at any time. a broken link is caused by signal loss. this may occur because of a cable break, or because of an interruption in the signal transmitted by the link partner. auto-negotiation resumes in an attempt to determine the new link configuration. if the management entit y re-starts auto-negotiation by setting the restart auto-negotiate bit of the basic control reg - ister , the lan8710a/lan8710ai will respond by stopping all tr ansmission/receiving operations. once the break_link_ - timer is completed in the auto-negotiation state-machine ( approximately 1200ms), auto-negotiation will re-start. in this case, the link partner will have also dropped the link due to lack of a received signal, so it too will resume auto-negoti - ation. downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 24 ? 2016 microchip technology inc. 3.2.3 disabling auto-negotiation auto-negotiation can be disabled by setting the auto-negotiation enable bit of the basic control register to zero. the device will then force its speed of operat io n to reflect the information in the basic control register ( speed select bit and duplex mode bit). these bits should be ignored when auto-negotiation is enabled. 3.2.4 half vs. full duplex half duplex operation relies on the csma/cd (carrier sense multiple access / collision detect) protocol to handle net - work traffic and collisions. in this mode, the carrier sense si gnal , crs, responds to both transmit and receive activity. if data is received while the transceiver is transmitting, a collision results. in full duplex mode, the transceiver is able to transmit a nd receive data simultaneously. in this mode, crs responds only to receive activity. the csma/cd protocol does not apply and collision detection is disabled. 3.3 hp auto-mdix support hp auto-mdix facilitates the use of cat-3 (10base-t) or cat-5 (100base-t) media utp interconnect cable without consideration of interface wiri ng scheme. if a user plugs in either a direct connect lan cable, or a cross-over patch cable, as shown in figure 3-4 , the devices auto-mdix transceiver is cap abl e of configuring th e txp/txn and rxp/rxn pins for correct transceiver operation. the internal logic of the device detects the tx and rx pi ns of the connecting device. since the rx and tx line pairs are interchangeable, special pcb design considerations are needed to accommodate the symmetrical magnetics and termination of an auto-mdix design. the auto-mdix function can be disabled via the amdixctrl bit in the special control/status indications register . figure 3-4: direct cable connection vs. cross-over cable connection 12 3 4 5 6 7 8 txp txn rxp not used not used rxn not used not used 12 3 4 5 6 7 8 txp txn rxp not used not used rxn not used not used direct connect cable rj-45 8-pin straight-through for 10base-t/100base-tx signaling 12 3 4 5 6 7 8 txp txn rxp not used not used rxn not used not used 12 3 4 5 6 7 8 txptxn rxp not used not used rxn not used not used cross-over cable rj-45 8-pin cross-over for 10base-t/100base-tx signaling 3.4 mac interface the mii/rmii block is responsible for communication with the mac controller. special sets of hand-shake signals are used to indicate that valid received/transmitted data is present on the 4 bit receive/transmit bus. the device must be configured in mii or rmii mod e. this is done by specific pin strapping configurations. refer to sec - tion 3.4.2.3, "mii vs. rm ii configuration," on page 26 for information on pin strapping and how the pins are mapped differently. downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 25 lan8710a/lan8710ai 3.4.1 mii the mii includes 16 interface signals: transmit data - txd[3:0] transmit strobe - txen transmit clock - txclk transmit error - txer/txd4 receive data - rxd[3:0] receive strobe - rxdv receive clock - rxclk receive error - rxer/rxd4/phyad0 collision indication - col carrier sense - crs in mii mode, on the transmit path, the transceiver drives the transmit clock, txclk, to the controller. the controller syn - chronizes the transmit data to the rising edge of txclk. the controller drives txen high to indicate valid transmit data. the controller drives txer high when a transmit error is detected. on the receive path, the transceiver driv es both the receive data, rxd[3:0], and the rxclk signal. the controller clocks in the receive data on the rising edge of rxclk when the tr ansceiver drives rxdv high. the transceiver drives rxer high when a receive error is detected. 3.4.2 rmii the device supports the low pin count reduced media independen t interface (rmii) intended for use between ethernet transceivers and switch asics. u nder ieee 802.3, an mii comprised of 16 pins for data and control is defined. in devices incorporating many macs or transceiver interfaces such as s witches, the number of pins c an add significant cost as the port counts increase. rmii reduces this pin count while reta ining a management interface (m dio/mdc) that is identical to mii. the rmii interface has the following characteristics: it is capable of supporting 10mbps and 100mbps data rates a single clock reference is used for both transmit and receive it provides independent 2-bit (di-bit) wide transmit and receive data paths it uses lvcmos signal levels, compatible with common digital cmos asic processes the rmii includes the following interface signals (1 optional): transmit data - txd[1:0] transmit strobe - txen receive data - rxd[1:0] receive error - rxer (optional) carrier sense - crs_dv reference clock - (rmii references usually define this signal as ref_clk) 3.4.2.1 crs_dv - carrier sense/receive data valid the crs_dv is asserted by the device when the receive m edium is non-idle. crs_dv is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. in 10base-t mode when squelch is passed, or in 100base-x mode when 2 non-contiguous zeros in 10 bits are detected, the carrier is said to be detected. loss of carrier shall result in the deassertion of crs_dv synchronous to the cycle of ref_clk which presents the first di-bit of a nibble onto rxd[1:0] (for example, crs_dv is deasserted only on nibble boundaries). if the device has addi - tional bits to be presented on rxd[1:0] following the initial deassertion of crs_dv, then the device shall assert crs_dv on cycles of ref_clk which pres ent the second di-bit of each nibble and de-assert crs_dv on cycles of ref_clk which present the first di-bit of a nibble. the resu lt is, starting on nibble boundaries, crs_dv toggles at 25 mhz in 100mbps mode and 2.5 mhz in 10mbps mode when crs ends before rxdv (for ex ample, the fifo still has bits to transfer when the carrier event ends). theref ore, the mac can accurately recover rxdv and crs. during a false carrier event, crs_dv shall remain asserted for the duration of carrier acti vity. the data on rxd[1:0] is considered valid once crs_dv is asserted. however, since the assertion of crs_dv is asynchronous relative to ref_clk, the data on rxd[1:0] shall be 00 until proper receive signal decoding takes place. downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 26 ? 2016 microchip technology inc. 3.4.2.2 reference clock (ref_clk) the rmii ref_clk is a continuous clock that provides the timing reference for crs_dv, rxd[1:0], txen, txd[1:0] and rxer. the device uses ref_clk as the network clock such that no buffering is required on the transmit data path. however, on the receive data path, the receiver recovers the clock from the incoming data stream, and the device uses elasticity buffering to accommodate for differences between the recovered clock and the local ref_clk. 3.4.2.3 mii vs. rmii configuration the device must be configured to support the mii or rmii bus for connectivity to the mac. this configuration is done via the rmiisel configuration strap. mii or rmii mode select ion is configured based on the strapping of the rmiisel configuration strap as described in section 3.7.3, "rmii sel: mii/rmii mode conf iguration," on page 31 . most of the mii and rmii pin s are multiplexed. ta b l e 3-2 describes the relationship of the related device pins to the mii and rmii mode signal names. table 3-2: mii/rmii signal mapping pin name mii mode rmii mode txd0 txd0 txd0 txd1 txd1 txd1 txen txen txen rxer/ rxd4/phyad0 rxer rxer note 3-2 col/crs_dv/mode2 col crs_dv rxd0/mode0 rxd0 rxd0 rxd1/mode1 rxd1 rxd1 txd2 txd2 note 3-1 txd3 txd3 note 3-1 nint/txer/txd4 txer/ txd4 crs crs rxdv rxdv rxd2/rmiisel rxd2 rxd3/phyad2 rxd3 txclk txclk rxclk/phyad1 rxclk xtal1/clkin xtal1/clkin ref_clk note 3-1 in rmii mode, this pin needs to tied to vss. note 3-2 t he rxer signal is optional on the rmii bus. this signal is required by the transceiver, but it is optional for the mac. the mac can choose to ignore or not use this signal. downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 27 lan8710a/lan8710ai 3.5 serial management interface (smi) the serial management interface is used to control the device and obtain its status. this interface supports registers 0 through 6 as required by clause 22 of the 802.3 standard, as we ll as vendor-specific registers 16 to 31 allowed by the specification. non-supported registers (such as 7 to 15) will be read as hexadecimal ffff. device registers are detailed in section 4.0, "register descriptions," on page 43 . at the system level, smi provides 2 si gnals: mdio and mdc. the mdc signal is an aperio dic clock provided by the station management controller (smc). mdio is a bi-directional data smi input/output signal that receives serial data (commands) from the controller smc and sends serial data (status) to the smc. the minimum time between edges of the mdc is 160 ns. there is no maximu m time between edges. the minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400 ns. these modest timing requirements allow this interface to be easily driven by the i/o port of a microcontroller. the data on the mdio line is latched on the rising edge of the mdc. th e frame structure and ti ming of the data is shown in figure 3-5 and figure 3-6 . the timing relationships of the mdio signals are further described in section 5.5.6, "smi timing," on page 64 . figure 3-5: mdc mdio read cycle ... 32 1's 0110a4a3a2a1a0r4r3r2r1r0 d1 ... d15 d14 d0 preamble start of frame op code phy address register address turn around data data from phy data to phy mdio timing and frame structure - read cycle figure 3-6: mdc mdio ... 32 1's 0 1 1 0 a4a3a2a1a0r4r3r2r1r0 write cycle d15 d14 d1 d0 ... data preamble start of frame op code phy address register address turn around data to phy mdio timing and frame structure - write cycle 3.6 interrupt management the device management interface supports an interrupt capability that is not a part of the ieee 802.3 specif ication. this interrupt capability generates an active low asynchronous interrupt signal on the nint output whenever certain events are detected as setup by the interrupt mask register . the devices interrupt system provides two modes, a primary interrupt mode and an alternative inte rrupt mode. both systems will assert the nint pin low when the corresponding mask bit is set. these modes differ only in how they de- assert the nint interrupt output. these mode s are detailed in the following subsections. note: th e primary interrupt mode is the default interrupt mode after a power-up or hard reset. the alternative interrupt mode requires setup after a power-up or hard reset. downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 28 ? 2016 microchip technology inc. 3.6.1 primary interrupt system the primary interrupt system is the default interrupt mode ( altint bit of the mode control/status register is 0). the primary interrupt system is always selected after power-up or hard reset. in this mode, to set an interrupt, set the cor - responding mask bit in the interrupt mask register (see table 3-3 ). then when the event to assert nint is true, the nint output will be asserted. when the corresponding event to dea ssert nint is true, then the nint will be de-asserted. table 3-3: interrupt management table mask interrupt source flag interrupt source event to assert ni nt event to de-assert nint 30.7 29.7 energyon 17.1 energyon rising 17.1 ( note 3-3 ) falling 17.1 or reading register 29 30.6 29.6 auto-negotiation complete 1.5 auto-negotiate comple te rising 1.5 falling 1.5 or reading register 29 30.5 29.5 remote fault detected 1.4 remote fault rising 1.4 falling 1.4, or reading register 1 or reading register 29 30.4 29.4 link down 1.2 link status falling 1.2 reading register 1 or reading register 29 30.3 29.3 auto-negotiation lp ackn owledge 5.14 acknowledge rising 5.14 falling 5.14 or read register 29 30.2 29.2 parallel detection fa ult 6.4 parallel detec - tion fault rising 6.4 falling 6.4 or reading register 6, or reading register 29 or re-auto negotiate or link down 30.1 29.1 auto-negotiation page received 6.1 page received rising 6.1 falling of 6.1 or reading register 6, or reading register 29 re-auto negotiate, or link down. note 3-3 if the mask bit is enabled and nint has been de-a sserted while energyon is still high, nint will assert for 256 ms, approximately one second after energyon goes low when the cable is unplugged. to prevent an unexpected assertion of nint, the energyon interrupt mask should always be cleared as part of the energyon interrupt service routine. note: th e energyon bit in the mode control/status register is defaulted to a 1 at the start of the signal acqui - sition process, therefore the int7 bit in the interrupt mask register will also read as a 1 at power-up. if no signal is present, then both energyon and int7 will clear within a few milliseconds. 3.6.2 alternate interrupt system the alternate interrupt system is enabled by setting the altint bit of the mode control/status register to 1. in this mode, to set an interrupt, set the correspondi ng bit of the in the mask register 30, (see ta b l e 3-4 ). to clear an interrupt, either clear the corresponding bit in the interrupt mask register to deassert the nint output, or clear the interrupt source, and write a 1 to the corresponding interrupt source flag. writing a 1 to the interrupt source flag will cause the state machine to check the interrupt sour ce to determine if the interrupt source flag should clear or stay as a 1. if the condition to deassert is true, then the interrupt source flag is cleared and nint is also deasserted. if the condition to deassert is false, then the interrupt source flag remains set, and the nint remains asserted. downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 29 lan8710a/lan8710ai for example, setting the int7 bit in the interrupt mask register will enable the energyon interrupt. after a cable is plugged in, the energyon bit in the mode control/status register goes active and nint will be asserted low. to de- assert the nint interrupt output, either clear the energyon bit in the mode control/status register by removing the cable and then writing a 1 to the int7 bit in the interrupt mask register , or clear the int7 mask (bit 7 of the interrupt mask register ). table 3-4: alternative interrupt system management table mask interrupt source flag interrupt source event to ass ert nint condition to de-assert bit to cl ear nint 30.7 29.7 energyon 17.1 energyon rising 17.1 17.1 low 29.7 30.6 29.6 auto-negotiation com plete 1.5 auto-negotiate complete rising 1.5 1.5 low 29.6 30.5 29.5 remote fault de tected 1.4 remote fault rising 1.4 1.4 low 29.5 30.4 29.4 link down 1.2 link status falling 1.2 1.2 high 29.4 30.3 29.3 auto-negotiation lp acknowledge 5.14 acknowledge rising 5.14 5.14 low 29.3 30.2 29.2 parallel detec - tion fault 6.4 parallel detec - tion fault rising 6.4 6.4 low 29.2 30.1 29.1 auto-negotiation pa ge received 6.1 page received rising 6.1 6.1 low 29.1 note: th e energyon bit in the mode control/status register is defaulted to a 1 at the start of the signal acqui - sition process, therefore the int7 bit in the interrupt mask register will also read as a 1 at power-up. if no signal is present, then both energyon and int7 will clear within a few milliseconds. 3.7 configuration straps configuration straps allow various features of the device to be automatically configured to user defined values. config - uration straps are latched upon power-on reset (por) and pi n reset (nrst). configuration straps include internal resistors in order to prevent the signal fr om floating when unconnected. if a part icular configuration strap is connected to a load, an external pull-up or pull-down resistor should be used to augment the internal resistor to ensure that it reaches the required voltage level prior to latching. the in ternal resistor can also be overridden by the addition of an external resistor. note 3-4 the system designer must guarantee that configuration strap pins meet the timing requirements specified in section 5.5.3, "power-on nrst & configuration strap timing," on page 59 . if configuration strap pins are not at the correct voltage level prior to being latched, the device may capture incorrect strap values. note 3-5 w hen externally pulling configuration straps high, the strap should be tied to vddio, except for regoff and nintsel which should be tied to vdd2a. 3.7.1 phyad[2:0] : phy address configuration the phyad[2:0] configuration straps are driven high or low to give each phy a unique address. this address is latched into an internal register at the end of a hardware reset ( default = 000b). in a multi-tran sceiver application (such as a repeater), the controller is able to manage each transceiver via the uniq ue address. each transceiver checks each man - agement data frame for a matching address in the relevant bi ts. when a match is recognized, the transceiver responds to that particular frame. the phy address is also used to seed the scrambler. in a multi- transceiver application, this ensures that the scramblers are out of synchronization and disperses the electromagnetic radiation across the fre - quency spectrum. downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 30 ? 2016 microchip technology inc. the devices smi address may be configured using hardware configuration to any value between 0 and 7. the user can configure the phy address using software configuration if an address greater than 7 is required. the phy address can be written (after smi communication at some address is established) using the phyad bits of the special modes reg - ister . the phyad[2:0] configuration straps are multiple xed with other signals as shown in ta b l e 3-5 . table 3-5: pin names for address bits address bit pin name phyad[0] rxer/rxd4/ phyad0 phyad[1] rxclk/ phyad1 phyad[2] rxd3/ phyad2 3.7.2 mode[2:0] : mode configuration the mode[2:0] configuration straps control the configuration of the 10/100 digital block. when the nrst pin is deas - serted, the register bit values are loaded according to the mode[2:0] configuration straps. the 10/100 digital block is then configured by the register bit val ues. when a soft reset occurs via the soft reset bit of the basic control register , the configuration of the 10/100 digit al block is controlled by the register bit values and the mode[2:0] configuration straps have no affect. the devices mode may be configured using the h ardware configuration straps as summarized in table 3-6 . the user may configure the transceiver mode by writing the smi registers. downloaded from: http:///
table 3-6: mode[2:0] bus mode[2:0] mode definitions default register bit values register 0 register 4 [13,12,10,8] [8,7,6,5] 000 10base-t half duplex. auto-negotiation disabled. 0000 n/a 001 10base-t full duplex. auto-negotiation disabled. 0001 n/a 010 100base-tx half duplex. auto-negotiation dis - abled. crs is active during transmit & receive. 1000 n/a 011 100base-tx full duplex. auto-negotiation disabled. crs is active during receive. 1001 n/a 100 100base-tx half duplex is advertised. auto-negoti - ation enabled. crs is active during transmit & receive. 1100 0100 101 repeater mode. auto-negotiation enabled. 100 base-tx half duplex is advertised. crs is active during receive. 1100 0100 110 power down mode. in this mode the transceiver will wake-up in power-down mode. the transceiver cannot be used when the mode[2:0] bits are set to this mode. to exit this mode, the mode bits in reg - ister 18.7:5(see section 4.2.9, "special modes reg - ister," on page 50 ) must be configured to some other value and a soft reset must be issued. n/a n/a 111 all capable. auto-negotiation enabled. x10x 1111 ? 2016 microchip technology inc. ds00002164b-page 31 lan8710a/lan8710ai the mode[2:0] hardware configuration pins are multiplexed with other signals as shown in ta b l e 3-7 . table 3-7: pin names for mode bits mode bit pin name mode[0] rxd0/ mode0 mode[1] rxd1/ mode1 mode[2] col/crs_dv/ mode2 3.7.3 rmiisel : mii/rmii mode configuration mii or rmii mode selection is latched on the rising edge of the internal reset (nrst) based on the strapping of the rmi - isel configuration strap. the default mode is mii (via the in ternal pull-down resistor). to select rmii mode, pull the rmi - isel configuration strap high with an external resistor to vddio. when the nrst pin is deasserted, the miimode bit of the special modes register is loaded according to the rmiisel configuration strap. the m ode is reflected in the miimode bit of the special modes register . refer to section 3.4, "mac interface," on page 24 for additional information on mii and rmii modes. downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 32 ? 2016 microchip technology inc. 3.7.4 regoff : internal +1.2v regulator configuration the incorporation of flexpwr te chnology provides the ability to disable the in ternal +1.2v regulator. when the regulator is disabled, an external +1.2v must be supplied to the vddcr pin. disabling the internal +1.2v regulator makes it pos - sible to reduce total system power, since an external switching regulat or with greater efficiency (versus the internal linear regulator) can be used to provide +1.2v to the transceiver circuitry. note: because the regoff configuration strap shares f unctionality with the led1 pin, proper consideration must also be given to the led polarity. refer to section 3.8.1.1, "r egoff and led1 polarity selection," on page 33 for additional information on the relation between regoff and the led1 polarity. 3.7.4.1 disabling the internal +1.2v regulator to disable the +1.2v internal regulator, a pull-up strapping resistor should be connected from the regoff configuration strap to vdd2a. at power-on, after both vddio and vdd2a are within specification, the transceiver will sample regoff to determine whether the internal regulator should turn on. if the pin is sampled at a voltage greater than v ih , then the internal regulator is disabled and the system must supply +1.2v to the vddcr pin. the vddio voltage must be at least 80% of the operating voltage level (1.44v when o perating at 1.8v, 2.0v when op erating at 2.5v, 2.64v when operating at 3.3v) before voltage is applied to vddcr. as described in section 3.7.4.2 , when regoff is left floating or connected to vss, the internal regula tor is enabled and the system is not re quired to supply +1.2v to the vddcr pin. 3.7.4.2 enabling the internal +1.2v regulator the +1.2v for vddcr is supplied by the on-chip regulator unless the transceiver is configured for the regulator off mode using the regoff configuration strap as described in section 3.7.4.1 . by default, the internal +1.2v regulator is enabled when regoff is floating (due to the internal pull-down resistor). during power-on, if regoff is sampled below v il , then the internal +1.2v regulator will turn on and operate with power from the vdd2a pin. 3.7.5 nintsel : nint/txer/txd4 configuration the nint, txer, and txd4 functions share a common pin. ther e are two functional modes for this pin, the txer/txd4 mode and nint (interrupt) mode. the nintsel configuration strap is latched at por and on the rising edge of the nrst. by default, nintsel is configured for nint mode via the internal pull-up resistor. note: because the nintsel configuration strap shares f unctionality with the led2 pin, proper consideration must also be given to the led polarity. refer to section 3.8.1.2, "nintsel and led2 polarity selection," on page 33 for additional information on the relation between nintsel and the led2 polarity. 3.8 miscellaneous functions 3.8.1 leds two led signals are provided as a conven ient means to determine the transceiver's mode of operation. all led signals are either active high or active low as described in section 3.8.1.2, "nintsel and led2 polarity selection" and section 3.8.1.1, "regoff and led1 polarity selection," on page 33 . the led1 output is driven active whenever the device detect s a valid link, and blinks when crs is active (high) indicat - ing activity. the led2 output is driven active when the operating speed is 100mbps. this led will go inactive when the operating speed is 10mbps or during line isolation. note: when pulling the led1 and led2 pins high, they must be tied to vdd2a, not vddio. downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 33 lan8710a/lan8710ai 3.8.1.1 regoff and led1 polarity selection the regoff configuration strap is shared with the led1 pin. the led1 output will automatically change polarity based on the presence of an external pull-up resistor. if the led1 pi n is pulled high to vdd2a by an external pull-up resistor to select a logical high for regoff , then the led1 output will be active low. if the led1 pin is pulled low by the internal pull-down resistor to select a logical low for regoff , the led1 output will then be an active high output. figure 3-7 details the led1 polarity for each regoff configuration. figure 3-7: led1/ regoff polarity configuration led1/regoff ~270 ohms regoff = 0 (regulator on) led output = active high ~270 ohms vdd2a regoff = 1 (regulator off) led output = active low led1/regoff 10k note: refer to section 3.7.4, "regoff: internal +1.2v regulator configuration," on page 32 for additional infor - mation on the regoff configuration strap. 3.8.1.2 nintsel and led2 polarity selection the nintsel configuration strap is shared wit h the led2 pin. the led2 output wil l automatically change polarity based on the presence of an external pull-down resistor. if the led2 pin is pulled high to vdd2a to select a logical high for nintsel , then the led2 output will be active low. if the led2 pin is pulled low by an external pull-down resistor to select a logical low for nintsel , the led2 output will then be an active high output. figure 3-8 details the led2 polarity for each nintsel configuration. figure 3-8: led2/ nintsel polarity configuration ~270 ohms nintsel = 0 led output = active high 10k ~270 ohms vdd2a nintsel = 1 led output = active low led2/nintsel led2/nintsel note: refer to section 3.7.5, "nintsel: nint/txer/txd4 configuration," on page 32 for additional information on the nintsel configuration strap. downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 34 ? 2016 microchip technology inc. 3.8.2 variable voltage i/o the devices digital i/o pins are variable voltage, allowing them to take advantage of low power savings from shrinking technologies. these pins can operate from a low i/o voltage of +1.62v up to +3.6v. the applied i/o voltage must main - tain its value with a tolerance of 10%. varying the voltage up or down after the transceiver has completed power-on reset can cause errors in the transceiver operation. refer to section 5.0, "operational characteristics," on page 54 for additional information. note: input signals must not be driven high before power is applied to the device. 3.8.3 power-down modes there are two device power-down modes: general power-d own mode and energy detect power-down mode. these modes are described in the following subsections. 3.8.3.1 general power-down this power-down mode is controlled via the power down bit of the basic control register . in this mode, the entire trans - ceiver (except the management interface) is powere d-down and remains in this mode as long as the power down bit is 1. when the power down bit is cleared, the transceiver pow ers up and is automatically reset. 3.8.3.2 energy detect power-down this power-down mode is activated by setting the edpwrdown bit of the mode control/status register . in this mode, when no energy is present on the line the transceiver is powered down (except for th e management interface, the squelch circuit, and the energyon logic). the energyon lo gic is used to detect the presence of valid energy from 100base-tx, 10base-t, or auto-negotiation signals. in this mode, when the energyon bit of the mode control/status register is low, the transceiver is powered-down and nothing is transmitted. when energy is received via link pulses or packets, the energyon bit goes high and the transceiver powers-up. the device automatic ally resets into the state prior to power-down and asserts the nint interrupt if the energyon interrupt is enabled in the interrupt mask register . the first and possibly the second packet to acti - vate energyon may be lost. when the edpwrdown bit of the mode control/status register is low, energy detect power-down is disabled. 3.8.4 isolate mode the device data paths may be electrically is olated from the mii/rmii interface by setting the isolate bit of the basic con - trol register to 1. in isolation mode, the tr ansceiver does not respond to the tx d, txen and txer inputs, but does respond to management transactions. isolation provides a means for multiple transceivers to be connected to the same mii/rmii interface without contention. by default, the transceiver is not isolated (on power-up ( isolate =0). 3.8.5 resets the device provides two forms of reset: hardware and software. the device registers are reset by both hardware and software resets. select register bits, i ndicated as nasr in the register definiti ons, are not cleared by a software reset. the registers are not reset by t he power-down modes described in section 3.8.3 . note: for the first 16us after coming out of reset, the mii/rmii interface will run at 2.5 mhz. after this time, it will switch to 25 mhz if auto-negotiation is enabled. 3.8.5.1 hardware reset a hardware reset is asserted by driving the nrst input pin low. when driven, nrst should be held low for the minimum time detailed in section 5.5.3, "power-on nrst & configuration strap timing," on page 59 to ensure a proper trans - ceiver reset. during a hardware reset, an external clock must be supplied to the xtal1/clkin signal. note: a hardware reset (nrst assertion) is required following power-up. refer to section 5.5.3, "power-on nrst & configuration strap timing," on page 59 for additional information. 3.8.5.2 software reset a software reset is ac tivated by setting the soft reset bit of the basic control register to 1. all registers bits, except those indicated as nasr in the register defin itions, are cleared by a software reset. the soft reset bit is self-clearing. per the ieee 802.3u standard, clause 22 (22.2.4.1.1) the reset process will be completed within 0.5s from the setting of this bit. downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 35 lan8710a/lan8710ai 3.8.6 carrier sense the carrier sense (crs) is output on the crs pin in mii mode, and the crs_dv pin in rmii mode. crs is a signal defined by the mii specificatio n in the ieee 802.3u standard. the device asserts crs based only on receive activity whenever the transceiver is either in repeater mode or full-duplex mode. otherwise the transceiver asserts crs based on either transmit or receive activity. the carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. it activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span. carrier sense terminates if a span of 10 con - secutive ones is detected before a /j/k/ start-of stream delimiter pair. if an ssd pair is detected, carrier sense is asserted until either /t/r/ endCof-stream delimiter pair or a pair of idle symbols is detected. carrier is negated after the /t/ symbol or the first idle. if /t/ is not followed by /r/, then carrier is maintained. carrier is treated similarly for i dle followed by some non-idle symbol. 3.8.7 collision detect a collision is the occurrence of simultaneous transmit and rece ive operations. the col output is asserted to indicate that a collision has been detected. col remains active for th e duration of the collision. col is changed asynchronously to both rxclk and txclk. the col output becom es inactive during full duplex mode. the col may be tested by setting the collision test bit of the basic control register to 1. this enables the collision test. col will be asserted within 512 bit times of txen rising and will be de-asserted within 4 bit times of txen falling. 3.8.8 link integrity test the device performs the link integrity test as outlined in the ieee 802.3u (clause 24-15) link m onitor state diagram. the link status is multiplexed with the 10mbps link status to form the link status bit in the basic status register and to drive the link led (led1). the dsp indicates a valid mlt-3 waveform present on the rxp and rxn signals as defined by the ansi x3.263 tp- pmd standard, to the link monitor st ate-machine, using the internal data_valid signal. when data_valid is asserted, the control logic moves into a link-ready state and waits for an enable from the auto-negotiation block. when received, the link-up state is entered, and the transmit and receive logic blocks become active. should auto-negoti - ation be disabled, the link integrity logic moves immediat ely to the link-up state when the data_valid is asserted. to allow the line to stabilize, the link integrity logic will wait a minimum of 330 ? sec from the time data_valid is asserted until the link-ready state is entered. should the data_valid input be negated at any time, this logic will immediately negate the link signal and enter the link-down state. when the 10/100 digital blo ck is in 10base-t mode, the link status is derived from the 10base-t receiver logic. 3.8.9 loopback operation the device may be configured for near-end loopback and far loopback. these loopback modes are detailed in the fol - lowing subsections. 3.8.9.1 near-end loopback near-end loopback mode sends the digital transmit data back out the receive data signals for testing purposes, as indi - cated by the blue arrows in figure 3-9 . the near-end loopback mode is enabled by setting the loopback bit of the basic control register to 1. a large percentage of the digital circuitry is operational in near-end loopback mode because data downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 36 ? 2016 microchip technology inc. is routed through the pcs and pma layers into the pmd sublay er before it is looped back. the col signal will be inac - tive in this mode, unless collision test is enabled in the basic control register . the transmitters are powered down regardless of the state of txen. figure 3-9: near-end loopback block diagram smsc ethernet transceiver 10/100 ethernet mac cat-5 xfmr digital rxd txd analog rx tx xx 3.8.9.2 far loopback far loopback is a special test mode for mdi (analog) loopback as indicated by the blue arrows in figure 3-11 . the far loopback mode is enabled by setting the farloopback bit of the mode control/status register to 1. in this mode, data that is received from the link partner on the mdi is looped back out to the link partner. the digital interface signals on the local mac interface are isolated. figure 3-10: far lo opback block diagram far-end system smsc ethernet transceiver 10/100 ethernet mac cat-5 xfmr digital rxd txd analog rx tx link partner xx note: this special test mode is only available when operating in rmii mode. downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 37 lan8710a/lan8710ai 3.8.9.3 connector loopback the device maintains reliable transmission over very short cables, and can be tested in a connector loopback as shown in figure 3-11 . an rj45 loopback cable can be used to route the tr ansmit sign als an the output of the transformer back to the receiver inputs, and this loopback will work at both 10 and 100. figure 3-11: connector loopback block diagram smsc ethernet transceiver 10/100 ethernet mac xfmr digital rxd txd analog rx tx 12 3 4 5 6 7 8 rj45 loopback cable. created by connecting pin 1 to pin 3 and connecting pin 2 to pin 6. 3.9 application diagrams this section provides typical appl ication diagrams for the following: simplified system level application diagram power supply diagram (1.2v supplied by internal regulator) power supply diagram (1.2v supplied by external source) twisted-pair interface diagram (single power supply) twisted-pair interface diagram (dual power supplies) downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 38 ? 2016 microchip technology inc. 3.9.1 simplified system l evel application diagram figure 3-12: simplified system level application diagram lan8710a/lan8710ai 10/100 phy 32-qfn mii txp txn mag rj45 rxp rxn 25mhz xtal1/clkin xtal2 txd[3:0] 4 rxd[3:0]rxclk rxdv 4 mii led[2:1] 2 interface mdio mdc nint nrst txclk txer txen downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 39 lan8710a/lan8710ai 3.9.2 power supply diagram (1.2 v supplied by internal regulator) figure 3-13: power supply diagram (1 .2v supplied by internal regulator) lan8710a/lan8710ai 32-qfn rbias vss 12.1k vdd2a c bypass c bypass vdd1a vddio c bypass c f vdddio supply 1.8 - 3.3v power supply 3.3v vddcr led1/ regoff ~270 ohm core logic internal regulator ch.2 3.3v circuitry in out ch.1 3.3v circuitry 470 pf 1 uf downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 40 ? 2016 microchip technology inc. 3.9.3 power supply diagram (1.2 v supplied by external source) figure 3-14: power supply diagram (1.2v supplied by external source) lan8710a/lan8710ai 32-qfn rbias vss 12.1k vdd2a c bypass c bypass vdd1a vddio c bypass c f vdddio supply 1.8 - 3.3v power supply 3.3v vddcr led1/ regoff core logic internal regulator (disabled) ch.2 3.3v circuitry in out ch.1 3.3v circuitry vddcr supply 1.2v ~270 ohm 10k 470 pf 1 uf downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 41 lan8710a/lan8710ai 3.9.4 twisted-pair interface diagram (single power supply) figure 3-15: twisted-pair interface diagram (single power supply) magnetics lan8710a/lan8710ai 32-qfn vdd2a c bypass txp txn power supply 3.3v 12 3 4 5 6 7 8 1000 pf3 kv rj45 75 75 rxp rxn c bypass vdd1a c bypass 49.9 ohm resistors ferrite bead downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 42 ? 2016 microchip technology inc. 3.9.5 twisted-pair interface diagram (dual power supplies) figure 3-16: twisted-pair interf a ce diagram (dual power supplies) magnetics lan8710a/lan8710ai 32-qfn vdd2a c bypass txp txn power supply 3.3v 12 3 4 5 6 7 8 1000 pf3 kv rj45 75 75 rxp rxn c bypass vdd1a c bypass 49.9 ohm resistors power supply 2.5v - 3.3v downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 43 lan8710a/lan8710ai 4.0 register descriptions this chapter describes the various control and status regi sters (csrs). all registers follow the ieee 802.3 (clause 22.2.4) management register set. all functionality and bit def initions comply with these standards. the ieee 802.3 spec - ified register index (in decimal) is incl uded with each register definition, allowing for addressing of these registers via the serial management interface (smi) protocol. 4.1 register nomenclature table 4-1 describes the register bit attribute notation used throughout this document. table 4-1: register bit types register bit type notation register bit description r read: a re gister or bit with this attribute can be read. w read: a re gister or bit with this attribute can be written. ro read only: read only. writes have no effect. wo write only: if a register or bit is write-only, reads will return unspecified data. wc write one to clear: writ ing a one clears the value. writing a zero has no effect wac write anything to clear: writing anything clears the value. rc read to clear: co ntents is cleared after the read. writes have no effect. ll latch low: c lear on read of register. lh latch high: clear on read of register. sc self-clearing: cont ents are self-cleared after the being set. writes of zero have no effect. contents can be read. ss self-setting: con tents are self-setting after being cleared. writes of one have no effect. contents can be read. ro/lh read only, latch high: bit s with this attribute will stay high until the bit is read. after it is read, the bit will either remain high if the high condition remains, or will go low if the high condition has been removed. if the bit has not been read, the bit will remain high regardless of a change to the high condition. this mode is used in some ethernet phy registers. nasr not affected by software reset. the state of nasr bits do not change on assertion of a software reset. reserved reserved field: reserved fields must be written with zeros to ensure future compati - bility. the value of reserved bits is not guaranteed on a read. many of these register bit notations can be comb ined. some examples of this are shown below: r/ w: can be written. will return current setting on a read. r/ wac: will return current setting on a read. writing anything clears the bit. 4.2 control and status registers table 4-2 provides a list of supported registers. register details , including bit definitions, are provided in the proceeding subsections. downloaded from: http:///
table 4-2: smi register map register index (decimal) register name group 0 basic control register basic 1 basic status register basic 2 phy identifier 1 extended 3 phy identifier 2 extended 4 auto-negotiation advertisement register extended 5 auto-negotiation link p artner ability register extended 6 auto-negotiation expansion register extended 17 mode control/status register vendor-specific 18 special modes vendor-specific 26 symbol error counter register vendor-specific 27 control / status indication register vendor-specific 29 interrupt source register vendor-specific 30 interrupt mask register vendor-specific 31 phy special control/status register vendor-specific lan8710a/lan8710ai ds00002164b-page 44 ? 2016 microchip technology inc. 4.2.1 basic control register index (in decimal): 0 size: 16 bits bits description type default 15 soft reset 1 = software reset. bit is self-clearing. when setting this bit do not set other bi ts in this register. the configuration (as described in section 3.7.2, mode[2:0]: mode configuration ) is set from the register bit values, and not from the mode pins. r/w sc 0b 14 loopback 0 = normal operation 1 = loopback mode r/w 0b 13 speed select 0 = 10mbps 1 = 100mbps ignored if auto-negotiation is enabled (0.12 = 1). r/w note 4-1 12 auto-negotiation enable 0 = disable auto-negotiate process 1 = enable auto-negotiate process (overrides 0.13 and 0.8) r/w note 4-1 downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 45 lan8710a/lan8710ai note 4-1 the default value of this bit is determined by the mode[2:0] configuration straps. refer to section 3.7.2, mode[2:0]: mode configuration for additional information. 4.2.2 basic status register index (in decimal): 1 size: 16 bits 11 power down 0 = normal operation 1 = general power down mode the auto-negotiation enable must be cleared before setting the power do wn. r/w 0b 10 isolate 0 = normal operation 1 = electrical isolation of phy from the mii/rmii r/w 0b 9 restart auto-negotiate 0 = normal operation 1 = restart auto-negotiate process bit is self-clearing. r/w sc 0b 8 duplex mode 0 = half duplex 1 = full duplex ignored if auto-negotiation is enabled (0.12 = 1). r/w note 4-1 7 collision test 0 = disable col test 1 = enable col test r/w 0b 6:0 reserved ro bits description type default 15 100base-t4 0 = no t4 ability 1 = t4 able ro 0b 14 100base-tx full duplex 0 = no tx full duplex ability 1 = tx with full duplex ro 1b 13 100base-tx half duplex 0 = no tx half duplex ability 1 = tx with half duplex ro 1b 12 10base-t full duplex 0 = no 10mbps with full duplex ability 1 = 10mbps with full duplex ro 1b 11 10base-t half duplex 0 = no 10mbps with half duplex ability 1 = 10mbps with half duplex ro 1b bits description type default downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 46 ? 2016 microchip technology inc. 4.2.3 phy identi fier 1 register index (in decimal): 2 size: 16 bits bits description type default 15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique identifier (o ui), respectively. r/w 0007h 4.2.4 phy identi fier 2 register index (in decimal): 3 size: 16 bits 10 100base-t2 full duplex 0 = phy not able to perf orm full duplex 100b ase-t2 1 = phy able to perform full duplex 100base-t2 ro 0b 9 100base-t2 half duplex 0 = phy not able to perf orm half duplex 100b ase-t2 1 = phy able to perform half duplex 100base-t2 ro 0b 8 extended status 0 = no extended status information in register 15 1 = extended status information in register 15 ro 0b 7:6 reserved ro 5 auto-negotiate complete 0 = auto-negotiate process not completed 1 = auto-negotiate process completed ro 0b 4 remote fault 1 = remote fault condition detected 0 = no remote fault ro/lh 0b 3 auto-negotiate ability 0 = unable to perform auto-negotiation function 1 = able to perform auto-negotiation function ro 1b 2 link status 0 = link is down 1 = link is up ro/ll 0b 1 jabber detect 0 = no jabber condition detected 1 = jabber condition detected ro/lh 0b 0 extended capabilities 0 = does not support extended capabilities registers 1 = supports extended capabilities registers ro 1b bits description type default downloaded from: http:///
bits description type default 15:10 phy id number assigned to the 19th through 24th bits of the oui. r/w 110000b 9:4 model number six-bit manufacturers model number. r/w 001111b 3:0 revision number four-bit manufacturers revision number. r/w note 4-2 ? 2016 microchip technology inc. ds00002164b-page 47 lan8710a/lan8710ai note 4-2 the default value of this field will vary dependent on the silicon revision number. 4.2.5 auto negotiation advertisement register index (in decimal): 4 size: 16 bits bits description type default 15:14 reserved ro 13 remote fault 0 = no remote fault 1 = remote fault detected r/w 0b 12 reserved ro 11:10 pause operation 00 = no pause 01 = symmetric pause 10 = asymmetric pause toward link partner 11 = advertise support for both symmetric pause and asymmetric pause to ward local device note: when both symmetric pause and asymmetric pause are set, the device will only be configured to, at most, one of the two set - tings upon auto-negotiation completion. r/w 00b 9 reserved ro 8 100base-tx full duplex 0 = no tx full duplex ability 1 = tx with full duplex r/w note 4-3 7 100base-tx 0 = no tx ability 1 = tx able r/w 1b 6 10base-t full duplex 0 = no 10mbps with full duplex ability 1 = 10mbps with full duplex r/w note 4-3 5 10base-t 0 = no 10mbps ability 1 = 10mbps able r/w note 4-3 downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 48 ? 2016 microchip technology inc. note 4-3 the default value of this bit is determined by the mode[2:0] configuration straps. refer to section 3.7.2, mode[2:0]: mode configuration for additional information. 4.2.6 auto negotiation link partner ability register index (in decimal): 5 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable note: this device does not support next page ability. ro 0b 14 acknowledge 0 = link code word not yet received 1 = link code word received from partner ro 0b 13 remote fault 0 = no remote fault 1 = remote fault detected ro 0b 12:11 reserved ro 10 pause operation 0 = no pause supported by partner station 1 = pause supported by partner station ro 0b 9 100base-t4 0 = no t4 ability 1 = t4 able note: this device does not support t4 ability. ro 0b 8 100base-tx full duplex 0 = no tx full duplex ability 1 = tx with full duplex ro 0b 7 100base-tx 0 = no tx ability 1 = tx able ro 0b 6 10base-t full duplex 0 = no 10mbps with full duplex ability 1 = 10mbps with full duplex ro 0b 5 10base-t 0 = no 10mbps ability 1 = 10mbps able ro 0b 4:0 selector field 00001 = ieee 802.3 ro 00001b 4:0 selector field 00001 = ieee 802.3 r/w 00001b bits description type default downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 49 lan8710a/lan8710ai 4.2.7 auto negotiation expansion register index (in decimal): 6 size: 16 bits bits description type default 15:5 reserved ro 4 parallel detection fault 0 = no fault detected by parallel detection logic 1 = fault detected by parallel detection logic ro/lh 0b 3 link partner next page able 0 = link partner does not have next page ability 1 = link partner has next page ability ro 0b 2 next page able 0 = local device does not have next page ability 1 = local device has next page ability ro 0b 1 page received 0 = new page not yet received 1 = new page received ro/lh 0b 0 link partner auto-negotiation able 0 = link partner does not have auto-negotiation ability 1 = link partner has auto-negotiation ability ro 0b 4.2.8 mode control/ status register index (in decimal): 17 size: 16 bits bits description type default 15:14 reserved ro 13 edpwrdown enable the energy detect power-down mode: 0 = energy detect power-down is disabled 1 = energy detect power-down is enabled r/w 0b 12:10 reserved ro 9 farloopback enables far loopback mode (for example, all the received packets are sent back simultaneously (in 100base-tx only)). this bit is only active in rmii mode. this mode works even if the isolate bit (0.10) is set. 0 = far loopback mode is disabled 1 = far loopback mode is enabled refer to section 3.8.9.2, far loopback for additional information. r/w 0b downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 50 ? 2016 microchip technology inc. 4.2.9 special modes register index (in decimal): 18 size: 16 bits bits description type default 15 reserved ro 14 miimode reflects the mode of the digital interface: 0 = mii mode 1 = rmii mode note: when writing to this register, the default value of this bit must always be written back. r/w nasr note 4-4 13:8 reserved ro 7:5 mode transceiver mode of operation. refer to section 3.7.2, mode[2:0]: mode configuration for additional details. r/w nasr note 4-5 4:0 phyad phy address. the phy address is used for the smi address and for initial - ization of the cipher (scrambler) key. refer to section 3.7.1, phyad[2:0]: phy address configuration for additional details. r/w nasr note 4-6 note 4-4 the d efault value of this field is determined by the rmiisel configuration strap. refer to section 3.7.3, rmiisel: mii/rmii mode configuration for additiona l information. note 4-5 the de fault value of this field is determined by the mode[2:0] configuration straps. refer to section 3.7.2, mode[2:0]: mode configuration for additional information. note 4-6 the de fault value of this field is determined by the phyad[2:0] configuration straps. refer to section 3.7.1, phyad[2:0]: phy address configuration for additiona l information. 8:7 reserved ro 6 altint alternate interrupt mode: 0 = primary interrupt system enabled (default) 1 = alternate interrupt system enabled refer to section 3.6, interrupt management for additional information. r/w 0b 5:2 reserved ro 1 energyon indicates whether energy is detected. this bit transitions to 0 if no valid e nergy is detected within 256ms. it is reset to 1 by a hardware reset and is unaffected by a software reset. refer to section 3.8.3.2, energy detect power-down for additional information. ro 1b 0 reserved r/w 0b bits description type default downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 51 lan8710a/lan8710ai 4.2.10 symbol error counter register index (in decimal): 26 size: 16 bits bits description type default 15:0 sym_err_cnt the symbol error counter increments whe never an invalid code symbol is received (including idle symbols) in 100base-tx mode. the counter is incremented only once per packet, even when the received packet contains more than one symbol error. this counter increments up to 65,536 (2 16 ) and rolls over to 0 after reaching the maximum value. note: this re gister is cleared on rese t, but is not cleared by reading the register. this register does not increment in 10base-t mode. ro 0000h 4.2.11 special control/stat us indications register index (in decimal): 27 size: 16 bits bits description type default 15 amdixctrl hp auto-mdix control: 0 = enable auto-mdix 1 = disable auto-mdix (use 27.13 to control channel) r/w 0b 14 reserved ro 13 ch_select manual channel select: 0 = mdi (tx transmits, rx receives) 1 = mdix (tx receives, rx transmits) r/w 0b 12 reserved ro 11 sqeoff disable the sqe test (heartbeat): 0 = sqe test is enabled 1 = sqe test is disabled r/w nasr 0b 10:5 reserved ro 4 xpol polarity state of the 10base-t: 0 = normal polarity 1 = reversed polarity ro 0b 3:0 reserved ro 4.2.12 interrupt source flag register index (in decimal): 29 size: 16 bits downloaded from: http:///
bits description type default 15:8 reserved ro 7 int7 0 = not source of interrupt 1 = energyon generated ro/lh 0b 6 int6 0 = not source of interrupt 1 = auto-negotiation complete ro/lh 0b 5 int5 0 = not source of interrupt 1 = remote fault detected ro/lh 0b 4 int4 0 = not source of interrupt 1 = link down (link status negated) ro/lh 0b 3 int3 0 = not source of interrupt 1 = auto-negotiation lp acknowledge ro/lh 0b 2 int2 0 = not source of interrupt 1 = parallel detection fault ro/lh 0b 1 int1 0 = not source of interrupt 1 = auto-negotiation page received ro/lh 0b 0 reserved ro 0b lan8710a/lan8710ai ds00002164b-page 52 ? 2016 microchip technology inc. 4.2.13 interrupt mask register index (in decimal): 30 size: 16 bits bits description type default 15:8 reserved ro 7:1 mask bits 0 = interrupt source is masked 1 = interrupt source is enabled note: re fer to section 4.2.12, interrupt source flag register for details on the corresponding interrupt definitions. r/w 0000000b 0 reserved ro downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 53 lan8710a/lan8710ai 4.2.14 phy special control/status register index (in decimal): 31 size: 16 bits bits description type default 15:13 reserved ro 12 autodone auto-negotiation done indication: 0 = auto-negotiation is not done or disabled (or not active) 1 = auto-negotiation is done ro 0b 11:7 reserved r/w 6 enable 4b5b 0 = bypass encoder/decoder 1 = enable 4b5b encoding/decoding. mac interface must be configured in mii mode. r/w 1b 5 reserved ro 4:2 speed indication hcdspeed value: 001 = 10base-t half-duplex 101 = 10base-t full-duplex 010 = 100base-tx half-duplex 110 = 100base-tx full-duplex ro xxx 1:0 reserved ro downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 54 ? 2016 microchip technology inc. 5.0 operational characteristics 5.1 absolute maximum ratings* supply voltage (vddio, vdd1a, vdd2a) ( note 5-1 ) ............................................................................... -0.5v to +3.6v digital core supply voltage (vddcr) ( note 5-1 ) ...................................................................................... -0.5v to +1.5v ethernet magnetics supply voltage .............................................................................................. .. ........... -0.5v to +3.6v positive voltage on signal pins, with respect to ground ( note 5-2 )..............................................................................+6v negative voltage on signal pins, with respect to ground ( note 5-3 ) ......................................................................... -0.5v positive voltage on xtal1/clkin, with respect to ground .................................................... .................... ... ...........+3.6v positive voltage on xtal2, with respect to ground ................................................................... ........... ... .................+2.5v ambient operating temperature in still air (t a ) ............................................................................................... note 5-4 0 storage temperature................................................................................................... ........... ............... .-55 o c to +150 o c junction to ambient ( ? ja ) ................................................................................................................................... .48.3 c/w junction to case ( ? jc )...................................................................................................................................... .1 0.6 o c/w lead temperature range ........................................................................................... refer to jedec sp ec. j-std-020 hbm esd performance per jedec jesd22-a114............................................................................. ......... ... ...class 3a iec61000-4-2 contact disc harg e esd performance ( note 5-5 ) ............................................................................+/-8kv iec61000-4-2 air-gap discharge esd performance ( note 5-5 ) ..........................................................................+/-15kv latch-up performance per eia/jesd 78........................................................................................... .. ............. .+/-150ma note 5-1 when powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is suggested that a clamp circuit be used. note 5-2 this rat ing does not apply to the following pins: xtal1/clkin, xtal2, rbias. note 5-3 this rat ing does not apply to the following pins: rbias. note 5-4 0 o c to +85 o c for extended commercial version, -40 o c to +85 o c for industrial version. note 5-5 perf ormed by independent 3rd party test facility. *stresses exceeding those listed in this section could cause permanent damage to the device. this is a stress rating onl y. exposure to absolute maximum rating conditions for extended periods may affect device reliability. functional operation of the device at any condition exceeding those indicated in section 5.2, "operating conditions**" , section 5.1, "absolute maximum ratings*" , or any other applicable section of this specification is not implied. note, device signals are not 5 volt tolerant unless specified otherwise. 5.2 operating conditions** supply voltage (vddio)......................................................................................................... ................. +1.62v to +3.6v analog port supply voltage (vdd1a, vdd2a) .................................................................................... .. . .. +3.0v to +3.6v digital core supply voltage (vddcr) .................................... ................................................... ..... . ..... +1.08v to +1.32v ethernet magnetics supply voltage .............................................................................................. .. ........ +2.25v to +3.6v ambient operating temperature in still air (t a ) ................................................................................................. note 5-4 **proper operation of the device is guaranteed only within t he ra nges specified in this section. after the device has com - pleted power-up, vddio and the magnetics power supply must maintain their voltage level with +/-10%. varying the volt age greater than +/-10% after the device has comp leted power-up can cause errors in device operation. note: do not drive input signals without power supplied to the device. downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 55 lan8710a/lan8710ai 5.3 power consumption this section details the device power measurements tak en over various operating conditions. unless otherwise noted, all measurements were taken with power supplies at nominal values (vddio, vdd1a, vdd2a = 3.3v, vddcr = 1.2v). see section 3.8.3, power-down modes for a description of the power down modes. table 5-1: device only current consumption and power dissipation power pin group vdda3.3 power pins(ma) vddcr power pin(ma) vddio power pin(ma) total cur rent (ma) total power (mw) 100base-tx /w traffic max 28 21 5.2 54 176 typical 26 18 4.3 48 158 min 23 18 2.4 43 101 note 5-8 10base-t /w traffic max 10.2 12.9 0.98 24.1 79.5 typical 9.4 11.4 0.4 21.2 70 min 9.2 10.9 0.3 20.4 44 note 5-8 energy detect power down max 4.5 3 0.3 7.8 25 typical 4.3 1.4 0.2 5.9 19.5 min 3.9 1.3 0 5.2 15.9 note 5-8 general power down max 0.4 2.6 0.3 3.3 10.9 typical 0.3 1.2 0.2 1.7 5.6 min 0.3 1.1 0 1.4 2.4 note 5-8 note 5-6 the curren t at vddcr is either supplied by the internal regulator from current entering at vdd2a, or from an external 1.2v supply when the internal regulator is disabled. note 5-7 cu rrent measurements do not include power applied to the magnetics or the optional external leds. the ethernet component current is typically 41ma in 100base-tx mode and 100ma in 10base-t mode, independent of the 2.5v or 3.3v supply rail of the transformer. note 5-8 ca lculated with full flexpwr features activat ed: vddio=1.8v & internal regulator disabled. downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 56 ? 2016 microchip technology inc. 5.4 dc specifications table 5-2: details the non-variable i/o buffer characteristics. th ese buffer types do not support variable voltage oper - ation. table 5-3: details the variable voltage i/o buffer characteristics. typical values are provided for 1.8v, 2.5v, and 3.3v vddio cases. table 5-2: non-variable i/o buffer characteristics parameter symbol min typ max units notes is type input buffer low input level high input level negative-going threshold positive-going threshold schmitt trigger hysteresis (v iht - v ilt ) input leakage (v in = vss or vddio) input capacitance v ili v ihi v ilt v iht v hys i ih c in -0.3 1.01 1.39 336 -10 1.19 1.59 399 3.6 1.39 1.79 459 10 2 vv v v mv ua pf schmitt trigger schmitt trigger note 5-9 o12 type buffers low output level high output level v ol v oh vdd2a - 0.4 0.4 vv i ol = 12ma i oh = -12ma iclk type buffer (xt al1 input) low input level high input level v ili v ihi -0.3 0.9 0.35 3.6 vv note 5-10 note 5-9 this specification applies to all inputs and tri-stated bi-directional pins. internal pull-down and pull-up resistors add +/- 50ua per-pin (typical). note 5-10 xt al1/clkin can optionally be driven from a 25mhz single-ended clock oscillator. downloaded from: http:///
table 5-3: variable i/o buffer characteristics parameter symbol min 1.8v typ 2.5v ty p 3.3v typ max units notes vis type input buffer low input level high input level neg-going threshold pos-going threshold schmitt trigger hyster - esis (v iht - v ilt ) input leakage (v in = vss or vddio) input capacitance v ili v ihi v ilt v iht v hys i ih c in -0.3 0.64 0.81 102 -10 0.83 0.99 158 1.15 1.29 136 1.41 1.65 138 3.6 1.76 1.90 288 10 2 vv v v mv ua pf schmitt trigger schmitt trigger note 5-11 vo8 type buffers low output level high output level v ol v oh vddio - 0.4 0.4 vv i ol = 8ma i oh = -8ma vod8 type buffer low output level v ol 0.4 v i ol = 8ma ? 2016 microchip technology inc. ds00002164b-page 57 lan8710a/lan8710ai note 5-11 this specification applies to all inputs and tri-stated bi-directional pins. internal pull-down and pull-up resistors add +/- 50ua per-pin (typical). table 5-4: 100base-tx transceiver characteristics parameter symbol min typ max units notes peak differential output voltage high v pph 950 1050 mvpk note 5-12 peak differential output voltage low v ppl -950 -1050 mvpk note 5-12 signal amplitude symmetry v ss 98 102 % note 5-12 signal rise and fall time t rf 3.0 5.0 ns note 5-12 rise and fall symmetry t rfs 0.5 ns note 5-12 duty cycle distortion d cd 35 50 65 % note 5-13 overshoot and undershoot v os 5 % jitter 1.4 ns note 5-14 note 5-12 measu red at line side of transformer, line replaced by 100 ? (+/- 1%) resistor. note 5-13 of fset from 16ns pulse width at 50% of pulse peak. downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 58 ? 2016 microchip technology inc. note 5-14 measured differentially. table 5-5: 10base-t tran sceiver characteristics parameter symbol min typ max units notes transmitter peak differential output voltage v out 2.2 2.5 2.8 v note 5-15 receiver differential squelch threshold v ds 300 420 585 mv note 5-15 min/ max voltages guaranteed as measured with 100 ? resistive load. 5.5 ac specifications this section details the various ac timing specifications of the device. note 5-16 the mii /smi timing adheres to the ieee 802.3 specification. refer to the ieee 802.3 specification for additional timing information. note 5-17 the rmi i timing adheres to the rmii consortium rmii specification r1.2. 5.5.1 equivalent test load output timing specifications assume a 25pf equivalent test load, unless otherwise noted, as illustrated in figure 5-1 below. figure 5-1: output eq uivalent test load 25 pf output downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 59 lan8710a/lan8710ai 5.5.2 power sequence timing this diagram illustrates the device power sequencing requi rements. the vddio, vdd1a, vdd2a and magnetics power supplies can turn on in any order provided they all reac h operational levels within the specified time period t pon . device power supplies can turn off in any order provided they all reach 0 volts within the specified time period p off . figure 5-2: power sequence timing vddio magnetics power t pon t poff vdd1a, vdd2a table 5-6: power sequence timing values symbol description min typ max units t pon power supply turn on time 50 ms t poff power supply turn off time 500 ms note: wh en the internal regulator is disabled, a powe r-up sequencing relationship exists between vddcr and the 3.3v power supply. for additional information refer to section 3.7.4, regoff: internal +1.2v regula - tor configuration . 5.5.3 power-on nrst & configuration strap timing this diagram illustrates the nrst reset and configuration st rap timing requirements in rela tion to power-on. a hardware reset (nrst assertion) is required following power-up. for proper operation, nrst must be asserted for no less than t rstia . the nrst pin can be asserted at any time, but must not be deasserted before t purstd after all external power sup - plies have reached 80% of their nominal operating levels. in o rder for valid configuration strap values to be read at power-up, the t css and t csh timing constraints must be followed. refer to section 3.8.5, resets for additional information. downloaded from: http:///
figure 5-3: power-on nrst & configuration strap timing t css nrst configuration strap pins input t rstia t csh configuration strap pins output drive t odad all external power supplies t purstd 80% t purstv t otaa table 5-7: power-on nrst & conf iguration strap timing values symbol description min typ max units t purstd external power supplies at 80% to nrst deassertion 25 ms t purstv external power supplies at 80% to nrst valid 0 ns t rstia nrst input assertion time 100 ? s t css configuration strap pins setup to nrst deassertion 200 ns t csh configuration strap pins hold after nrst deassertion 1 ns t otaa output tri-state after nrst assertion 50 ns t odad output drive after nrst deassertion 2 800 ( note 5- 20 ) ns lan8710a/lan8710ai ds00002164b-page 60 ? 2016 microchip technology inc. note 5-18 nrst deassertion must be monotonic. note 5-19 de vice configuration straps are latched as a result of nrst assertion. refer to section 3.7, configuration straps for details. configuration straps must only be pulled high or low and must not be driven as inputs. note 5-20 20 clock cycles for 25mhz, or 40 clock cycles for 50mhz. 5.5.4 mii interface timing this section specifies the mii interface transmit and receive timing. please refer to section 3.4.1, mii for additional details. downloaded from: http:///
figure 5-4: mii receive timing rxclk rxd[3:0] rxdv t clkh t clkl t clkp t val t hold t val t val t hold table 1.1 mii receive timing values symbol description min max units notes t clkp rxclk period note 5-21 ns t clkh rxclk high time t clkp *0.4 t clkp *0.6 ns t clkl rxclk low time t clkp *0.4 t clkp *0.6 ns t val rxd[3:0], rxdv output valid from rising edge of rxclk 28.0 ns note 5-22 t hold rxd[3:0], rxdv output hold from rising edge of rxclk 10.0 ns note 5-22 ? 2016 microchip technology inc. ds00002164b-page 61 lan8710a/lan8710ai note 5-21 40ns for 100base-tx operation, 400ns fo r 10base-t operation. note 5-22 t iming was designed for system load between 10 pf and 25 pf. downloaded from: http:///
figure 5-5: mii transmit timing txclk t su txd[3:0] txen t clkh t clkl t clkp t hold t su t hold t hold t su t hold table 5-8: mii transmit timing values symbol description min max units notes t clkp txclk period note 5-23 ns t clkh txclk high time t clkp *0.4 t clkp *0.6 ns t clkl txclk low time t clkp *0.4 t clkp *0.6 ns t su txd[3:0], txen setup time to rising edge of txclk 12.0 ns note 5-24 t hold txd[3:0], txen hold time after rising edge of txclk 0 ns note 5-24 lan8710a/lan8710ai ds00002164b-page 62 ? 2016 microchip technology inc. note 5-23 40ns for 100base-tx operation, 400ns for 10base-t operation. note 5-24 t iming was designed for system load between 10 pf and 25 pf. downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 63 lan8710a/lan8710ai 5.5.5 rmii interface timing figure 5-6: rmii timing clkin (ref_clk) rxd[1:0], rxer crs_dv t clkh t clkl t clkp t oval t ohold t oval t oval t ohold t su txd[1:0] txen t ihold t su t ihold t ihold t su t ihold table 5-9: rmii timing values symbol description min max units notes t clkp clkin period 20 ns t clkh clkin high time t clkp *0.35 t clkp *0.65 ns t clkl clkin low time t clkp *0.35 t clkp *0.65 ns t oval rxd[1:0], rxer, crs_dv output valid from ris - ing edge of clkin 14.0 ns note 5-25 t ohold rxd[1:0], rxer, crs_dv output hold from ris - ing edge of clkin 3.0 ns note 5-25 t su txd[1:0], txen setup time to rising edge of clkin 4.0 ns note 5-25 t ihold txd[1:0], txen input hold time after rising edge of clkin 1.5 ns note 5-25 note 5-25 timing was designed for system load between 10 pf and 25 pf. downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 64 ? 2016 microchip technology inc. 5.5.5.1 rmii clkin requirements table 5-10: rmii clkin (ref_clk) timing values parameter min typ max units notes clkin frequency 50 mhz clkin frequency drift 50 ppm clkin duty cycle 40 60 % clkin jitter 150 psec p-p C not rms 5.5.6 smi timing this section specifies the smi timing of the device. please refer to section 3.5, serial management interface (smi) for additional details. figure 5-7: smi timing mdc mdio t clkh t clkl t clkp t ohold mdio t su t ihold (data-out) (data-in) t ohold t val table 5-11: smi timing values symbol description min max units notes t clkp mdc period 400 ns t clkh mdc high time 160 (80%) ns t clkl mdc low time 160 (80%) ns t val mdio (read from phy) output valid from rising edge of mdc 300 ns t ohold mdio (read from phy) output hold from rising edge of mdc 0 ns t su mdio (write to phy) setup time to rising edge of mdc 10 ns t ihold mdio (write to phy) input hold time after rising edge of mdc 10 ns downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 65 lan8710a/lan8710ai 5.6 clock circuit the device can accept either a 25mhz crystal (preferred) or a 25mhz single-ended clock oscillator (50ppm) input. if the single-ended clock oscillator method is implemented, xtal2 should be left unconnected and xtal1/clkin should be driven with a nominal 0-3.3v clock signal. it is recommended that a crystal utilizing matching parallel l oad capacitors be used for the crystal input/output signals (xtal1/xtal2). either a 300uw or 100uw 25mhz crystal may be utilized. the 300uw 25mhz crystal specifications are detailed in section 5.6.1, "300uw 25mhz crystal specification," on page 65 . the 100uw 25mhz crystal specifications are detailed in section 5.6.2, "100uw 25mhz crystal specification," on page 66 . 5.6.1 300uw 25mhz crystal specification when utilizing a 300uw 25mhz crysta l, the following circuit design ( figure 5-8 ) and specifications ( table 5-12 ) are required to ensure proper operation. figure 5-8: 300uw 25mhz crystal circuit lan8710 xtal2 xtal1 y1 c 1 c 2 table 5-12: 300uw 25mhz crystal specifications parameter symbol min nom max units notes crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund 25.000 mhz frequency tolerance @ 25 o c f tol 50 ppm note 5-26 frequency stability over temp f temp 50 ppm note 5-26 frequency deviation over time f age +/-3 to 5 ppm note 5-27 total allowable ppm budget 50 ppm note 5-28 shunt capacitance c o 7 typ pf load capacitance c l 20 typ pf drive level p w 300 uw equivalent series resistance r 1 30 ohm operating temperature range note 5-35 +85 o c xtal1/clkin pin capacitance 3 typ pf note 5-30 xtal2 pin capacitance 3 typ pf note 5-30 downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 66 ? 2016 microchip technology inc. note 5-26 the maximum allowable values for frequency tolerance and frequency stability are application dependent. since any particular application must meet the ieee 50 ppm to tal ppm budget, the combination of these two values must be approximately 45 ppm (allowing for aging). note 5-27 freque ncy deviation over time is also referred to as aging. note 5-28 the tot al deviation for the tr ansmitter clock fre quency is specified by ieee 802.3u as ? 100 ppm. note 5-29 0 o c for extended commercial version, -40 o c for industrial version. note 5-30 this n umber includes the pad, the bond wire and the lead frame. pcb capacitance is not included in this value. the xtal1/clkin pin, xtal2 pi n and pcb capacitance values are required to accurately calculate the value of the two external load capacitors. the total load capacitance must be equivalent to what the crystal expects to see in the circuit so that the crystal oscillator will operate at 25.000 mhz. 5.6.2 100uw 25mhz crystal specification when utilizing a 100uw 25mhz crysta l, the following circuit design ( figure 5-9 ) and specifications ( table 5-13 ) are required to ensure proper operation. figure 5-9: 100uw 25mhz crystal circuit lan8710 xtal2 xtal1 r s y1 c 1 c 2 table 5-13: 100uw 25mhz crystal specifications parameter symbol min nom max units notes crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund 25.000 mhz frequency tolerance @ 25 o c f tol 50 ppm note 5-31 frequency stability over temp f temp 50 ppm note 5-31 frequency deviation over time f age 3 to 5 ppm note 5-32 total allowable ppm budget 50 ppm note 5-33 shunt capacitance c o 5 pf load capacitance c l 8 12 pf drive level p w 100 uw note 5-34 downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 67 lan8710a/lan8710ai note 5-31 the maximum allowable values for frequency tolerance and frequency stability are application dependent. since any particular application must meet the ieee 50 ppm total ppm budget, the combination of these two values must be approximately 45 ppm (allowing for aging). note 5-32 frequency deviation over time is also referred to as aging. note 5-33 the total deviation for the tr ansmitter clock fre quency is specified by ieee 802.3u as ? 100 ppm. note 5-34 the crystal must support 100uw operation to utilize this circuit. note 5-35 0 o c for extended commercial version, -40 o c for industrial version. note 5-36 this number includes the pad, the bond wire and the lead frame. pcb capacitance is not included in this value. the xtal1/clkin pin, xtal2 pi n and pcb capacitance values are required to accurately calculate the value of the two external load capacitors. the total load capacitance must be equivalent to what the crystal expects to see in the circuit so that the crystal oscillator will operate at 25.000 mhz. equivalent series resistance r 1 80 ohm xtal2 series resistor r s 495 500 505 ohm operating temperature range note 5-35 +85 o c xtal1/clkin pin capacitance 3 typ pf note 5-36 xtal2 pin capacitance 3 typ pf note 5-36 table 5-13: 100uw 25mhz crystal specifications (continued) parameter symbol min nom max units notes downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 68 ? 2016 microchip technology inc. 6.0 package information 6.1 32-qfn (punch) figure 6-1: 32-qfn package table 6-1: 32-q fn dimensions min nominal max remarks a 0.70 0.85 1.00 overall package height a1 0 0.02 0.05 standoff a2 0.65 0.90 mold cap thickness d/e 4.90 5.00 5.10 x/y body size d1/e1 4.55 4.75 4.95 x/y mold cap size d2/e2 3.20 3.30 3.40 x/y exposed pad size l 0.30 0.40 0.50 terminal length b 0.18 0.25 0.30 terminal width k 0.35 0.45 terminal to exposed pad clearance e 0.50 bsc terminal pitch note 1: all dime nsions are in millimeters unless otherwise noted. 2: dimen sion b applies to plated terminals and is meas ured between 0.15 and 0.30 mm from the terminal tip. 3: th e pin 1 identifier may vary, but is always located within the zone indicated. downloaded from: http:///
figure 6-2: 32-qfn recommended pcb land pattern ? 2016 microchip technology inc. ds00002164b-page 69 lan8710a/lan8710ai downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 70 ? 2016 microchip technology inc. 6.2 32-sqfn (sawn) figure 6-3: 32-sqfn package downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 71 lan8710a/lan8710ai 6.3 tape & reel information figure 6-4: taping dimens ions and part orientation figure 6-5: tape length and part quantity note: standard reel size is 5,000 pieces per reel. downloaded from: http:///
figure 6-6: reel dimensions lan8710a/lan8710ai ds00002164b-page 72 ? 2016 microchip technology inc. downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 73 lan8710a/lan8710ai 7.0 application notes 7.1 application diagram the device requires few external comp onents. the voltage on the magnetics center tap can range from 2.5 - 3.3v. 7.1.1 mii diagram figure 7-1: simplified application diagram lan8710 10/100 phy 32-qfn mii txp txn mag rj45 rxp rxn 25mhz xtal1/clkin xtal2 txd[3:0] 4 rxd[3:0] rxclk rxdv 4 mii led[2:1] 2 interface mdio mdc nint nrst txclk txer txen 7.1.2 power supply diagram downloaded from: http:///
figure 7-2: high-level syst em diagram for power lan8710 32-qfn rbias 32 vss 27 12.1k vdd1a nrst 19 c bypass 1 c bypass vdd2a vddcr vddio c bypass c f vdddio supply 1.8 - 3.3v analog supply 3.3v c 12 power to magnetics interface. r 6 1uf lan8710a/lan8710ai ds00002164b-page 74 ? 2016 microchip technology inc. 7.1.3 twisted-pair interface diagram figure 7-4: copper interface diagram magnetics lan8710 32-qfn 1 vdd2a c bypass 29 txp txn analog supply 3.3v 12 3 4 5 6 7 8 28 1000 pf3 kv rj45 75 75 31 rxp rxn 30 c bypass 27 vdd1a c bypass 49.9 ohm resistors magnetic supply 2.5 - 3.3v downloaded from: http:///
? 2016 microchip technology inc. ds00002165b-page 75 lan8710a/lan8710ai appendix a: data sheet revision history table a-1: revision history revision section/figure/entry correction rev b. (07-15-16) section 5.1, "absolute maxi - mum ratings*," on page 54 update to positive voltage on xtal1/clkin, with respe ct to ground. table 5-2, non-variable i/o buffer characteristics, on page 56 update to min/max values for the last row, iclk t ype buffer (xtal1 input) - high input level. rev. a (06-24-16) all document converted to microchip look and feel. rep laces smsc rev. 1.4 (08-23-12). section 5.2, "operating con - ditions**," on page 54 increased vddcr operational limits from +1.14v to +1.26v to +1.08v to +1.32v section 5.6, "clock circuit," on page 65 added new 100uw crystal specifications and circuit dia gram. the section is now split into two subsec - tions, one for 300uw crystals and the other for 100uw cryst als. section 6.0, "package infor - mation," on page 68 added new subsections to include sqfn package information. section , "product identifica - tion system," on page 77 updated ordering codes with sawn sqfn package options. rev. 1.4 (08-23-12) section 4.2.2, basic status register updated definitions of bits 10:8. section 4.2.14, "phy spe - cial control/status regis - ter," on page 53 updated bit 6 definition. cover ordering information modified. rev. 1.3 (04-20-11) cover added copper bond wire ordering codes to lan8710 ordering codes table 4.2.9, special modes register, on page 50 updated miimode bit description and added note: when writing to this register the default value of this bit must always be written back. section 3.7.3, "rmiisel: mii/rmii mode configura - tion," on page 31 updated second paragraph to: ? when the nrst pin is deasserted, the miimode bit of the special modes register is loaded accord - ing to the rmiisel configuration strap. the mode is reflected in the miimode bit of the special modes register . section 3.8.9.2, "far loop - back," on page 36 updated section to defeature information about register control of the mii/rmii mode. rev. 1.2 (11-10-10) section 5.5.5, "rmii inter - face timing," on page 63 updated diagrams and tables to include rxer. downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 76 ? 2016 microchip technology inc. the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con - tains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, late st microchip press releases, listing of semi - nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchips customer notification serv ice helps keep customers current on micr ochip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notifi - cation and follow the registration instructions. customer support users of microchip products can receiv e assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu - ment. technical support is available through the web site at: http://microchip.com/support downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 77 lan8710a/lan8710ai product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: lan8710a temperature range: -ezc = 0 ? c to +85 ? c (extended commercial) i-ezk = -40 ? c to +85 ? c (industrial) tape and reel option: blank = standard packaging (tray) tr = tape and reel (1) package: blank = punch package (32-qfn) abc = sawn package (32-sqfn) examples: a) lan8710ai-ezk-tr ? industrial temp., tape & reel, 32-qfn (punch) ? b) LAN8710A-EZC-abc ? ext. commercial temp., tray, 32-sqfn (sawn) note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the dev ice package. check with your microchip sa les office for package availability with the tape and reel option. part no. [x] temperature range device [x ] (1) tape & reel option - - [xxx] package downloaded from: http:///
lan8710a/lan8710ai ds00002164b-page 78 ? 2016 microchip technology inc. notes: downloaded from: http:///
? 2016 microchip technology inc. ds00002164b-page 79 lan8710a/lan8710ai information contained in this publication r egarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with yo ur specifications. microchip make s no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition , quality, performance, merchantability or fi tness for purpose . microchip disclaims all liabilit y arising from this information and its use. use of micro- chip devices in life support and/or safety applications is entirely at the buyer s risk, and the buyer agrees to defend, indemn ify and hold harmless microchip from any and all damages, claims, suits, or ex penses resulting from such use. no licenses are conveyed, impl icitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip l ogo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersyn ch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, body com, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit se rial programming, icsp, inter-c hip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of mi crochip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademarks of microc hip technology germany ii gmbh & co. kg, a subsidiary of microc hip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, prin ted in the u.s.a., all rights reserved. isbn: 978-1-5224-0779-9 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used in the intended manner and under normal conditions. there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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